公开(公告)号：US12217717B2

公开(公告)日：2025-02-04

申请号：US17756663

申请日：2022-04-19

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Zhaoxian Zhong

IPC: G09G3/36 ,  G09G3/3266

Abstract: The present disclosure relates to a circuit and a method for conditioning a clock signal, display panel, and display device. The circuit includes a signal conversion circuit and a delay processing circuit; when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, the delay processing circuit receives the N-th clock signal transmitted from the N-th clock signal output terminal, and performs delay processing on the N-th clock signal, so as to avoid occurrence of GOA-stage transfer abnormality when one of the plurality of CK clock signals is in an abnormal condition that no signal is output.

公开(公告)号：US20240161711A1

公开(公告)日：2024-05-16

申请号：US17756663

申请日：2022-04-19

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Zhaoxian Zhong

IPC: G09G3/36 ,  G09G3/3266

CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G2310/08

Abstract: The present disclosure relates to a circuit and a method for conditioning a clock signal, display panel, and display device. The circuit includes a signal conversion circuit and a delay processing circuit; when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, the delay processing circuit receives the N-th clock signal transmitted from the N-th clock signal output terminal, and performs delay processing on the N-th clock signal, so as to avoid occurrence of GOA-stage transfer abnormality when one of the plurality of CK clock signals is in an abnormal condition that no signal is output.