公开(公告)号：US20020014202A1

公开(公告)日：2002-02-07

申请号：US09820846

申请日：2001-03-30

Applicant: TDK CORPORATION

Inventor： Ko Onodera ,  Satoshi Kurimoto

IPC: B05C003/02

CPC classification number: H01G13/006 ,  Y10S156/922 ,  Y10S156/941 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T156/11 ,  Y10T156/17 ,  Y10T156/1702 ,  Y10T156/1707 ,  Y10T156/19 ,  Y10T156/1906

Abstract: The invention provides an electrode forming method with steps of arraying chip-style electronic components on an arraying flat bed thereby positioning and aligning the components, lowering a film coated with an adhesive in relative manner together with an adhering top plate parallel to the arraying flat bed thereby adhering ends of the positioned and aligned chip-style electronic components to the adhesive, then lowering the first film to which the chip-style electronic components are adhered in relative manner together with a coating top plate parallel to a coating flat bed provided with a conductive paste layer of a constant thickness thereby pressing the other ends of the chip-style electronic components to the coating flat bed and coating the ends of the electronic components with the conductive paste.

Abstract translation: 本发明提供了一种电极形成方法，该方法具有以下步骤：在阵列平板上排列芯片式电子部件，由此定位和对准部件，相对于平行于排列平板的粘合顶板，以相对的方式将涂覆有粘合剂的膜降低 从而将定位的和对准的芯片式电子部件的端部粘合到粘合剂上，然后将与芯片式电子部件粘附的第一膜相对于平行于涂覆平板的涂层顶板相对降低， 导电浆料层，从而将芯片式电子部件的另一端压入涂布平板，并用导电膏涂覆电子部件的端部。

公开(公告)号：US20040200577A1

公开(公告)日：2004-10-14

申请号：US10834000

申请日：2004-04-29

Applicant: TDK CORPORATION

Inventor： Ko Onodera ,  Satoshi Kurimoto

IPC: C09J001/00 ,  B32B031/00 ,  B32B001/00

CPC classification number: H01G13/006 ,  Y10S156/922 ,  Y10S156/941 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T156/11 ,  Y10T156/17 ,  Y10T156/1702 ,  Y10T156/1707 ,  Y10T156/19 ,  Y10T156/1906

Abstract: The invention provides an electrode forming method with steps of arraying chip-style electronic components on an arraying flat bed thereby positioning and aligning the components, lowering a film coated with an adhesive in relative manner together with an adhering top plate parallel to the arraying flat bed thereby adhering ends of the positioned and aligned chip-style electronic components to the adhesive, then lowering the first film to which the chip-style electronic components are adhered in relative manner together with a coating top plate parallel to a coating flat bed provided with a conductive paste layer of a constant thickness thereby pressing the other ends of the chip-style electronic components to the coating flat bed and coating the ends of the electronic components with the conductive paste.

Abstract translation: 本发明提供了一种电极形成方法，该方法具有以下步骤：在阵列平板上排列芯片式电子部件，由此定位和对准部件，相对于平行于排列平板的粘合顶板，以相对的方式将涂覆有粘合剂的膜降低 从而将定位的和对准的芯片式电子部件的端部粘合到粘合剂上，然后将与芯片式电子部件粘附的第一膜相对于平行于涂覆平板的涂层顶板相对降低， 导电浆料层，从而将芯片式电子部件的另一端压入涂布平板，并用导电膏涂覆电子部件的端部。