QUANTUM STATE PREPARATION CIRCUIT GENERATION METHOD AND APPARATUS, QUANTUM CHIP, AND ELECTRONIC DEVICE

    公开(公告)号:US20230351237A1

    公开(公告)日:2023-11-02

    申请号:US18202402

    申请日:2023-05-26

    CPC classification number: G06N10/20 G06N10/60

    Abstract: The present disclosure relates to a quantum state preparation circuit generation method and apparatus, a quantum chip, and an electronic device. The quantum chip may be applied to various intelligent terminals and on-board devices. The method includes: determining a first unitary operator respectively encoding rc qubits and rt qubits into a control register and a target register; acquiring at least two second unitary operators for performing phase shifting on the n qubits; determining a third unitary operator for replacing a qubit of the control register and a qubit of the target register; generating diagonal unitary matrix quantum circuits based on the first, second, third, fourth unitary operators, and a diagonal unitary matrix operator; combining the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniform control gates; and combining the at least two uniform control gates into a quantum state preparation circuit.

    METHOD FOR GENERATING QUANTUM STATE PREPARATION CIRCUIT, QUANTUM STATE PREPARATION METHOD, AND QUANTUM DEVICE

    公开(公告)号:US20230385673A1

    公开(公告)日:2023-11-30

    申请号:US18199474

    申请日:2023-05-19

    CPC classification number: G06N10/20

    Abstract: The present disclosure relates to a method for generating a quantum state preparation circuit, a quantum state preparation method, and a quantum device. The method includes: configuring, based on parameters of the quantum state preparation circuit, an input register for the quantum state preparation circuit and determining a number of auxiliary quantum bits; configuring a copy register and a target register according to the number of the auxiliary quantum bits; obtaining a diagonal unitary matrix quantum circuit by performing circuit construction through the input register, the copy register and the target register according to a quantum bit copy mode obtained based on a grid restriction condition; combining the diagonal unitary matrix quantum circuit and a single bit quantum gate to obtain at least one uniformly controlled gate circuit; and generating the quantum state preparation circuit based on the at least one uniformly controlled gate circuit.

    QUANTUM STATE PREPARATION CIRCUIT GENERATING METHOD AND SUPERCONDUCTING QUANTUM CHIP

    公开(公告)号:US20230080222A1

    公开(公告)日:2023-03-16

    申请号:US17985369

    申请日:2022-11-11

    Abstract: Provided are a quantum state preparation circuit generating method and apparatus, a superconducting quantum chip, and a storage medium. The method includes: configuring an input register storing n qubits, n being a positive integer; acquiring m ancilla qubits, m being a positive integer; configuring a copy register and a phase register storing m/2 ancilla qubits and m/2 ancilla qubits, respectively; processing qubits through the input register, the copy register, and the phase register, to obtain a diagonal unitary matrix quantum circuit; combining the diagonal unitary matrix quantum circuit and a single bit gate to obtain a uniform control matrix circuit; and combining different uniform control matrix circuits to obtain a quantum state preparation circuit.

    Quantum State Preparation Circuit Generation Method and Apparatus, Chip, Device, and Program Product

    公开(公告)号:US20230081903A1

    公开(公告)日:2023-03-16

    申请号:US18054724

    申请日:2022-11-11

    Abstract: A quantum state preparation circuit generation method and apparatus, a chip, a device, and a program product are provided, which relate to the field of quantum technology. The quantum state preparation circuit generation method includes: obtaining a target vector (21); generating a quantum state intermediate preparation circuit (22) for preparing the target vector on N qubits, the quantum state intermediate preparation circuit including N qubit uniform control gates, and N being a positive integer greater than or equal to 2; and converting each of the N qubit uniform control gates into a diagonal unitary matrix and a single bit gate, to obtain a quantum state preparation circuit (23) for preparing the target vector on the N qubits. This application can reduce a depth of a quantum state preparation circuit.

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