公开(公告)号：US3702986A

公开(公告)日：1972-11-14

申请号：US3702986D

申请日：1970-07-06

Applicant: TEXAS INSTRUMENTS INC

Inventor： TAYLOR FREDRICK JAMES ,  CHOATE WILLIAM C

IPC: G06F15/18

CPC classification number: G06N99/005

Abstract: A system is comprised of a series of trainable nonlinear processors in cascade. The processors are trained in sequence as follows. In a first phase of the sequence, a set of input signals comprising input information upon which the system is to be trained and a corresponding set of desired responses to these input signals are introduced into the first processor. When the first processor has been trained over the entire set, a second phase commences in which a second set of input signals along with the output of the first processor and corresponding set of desired responses are introduced into the second processor. During this second phase the input signals to the first and second processors are in sequential correspondence. In one embodiment of the invention the set of input signals to the first processor comprises the same set of input signals being introduced into the second processor delayed by a fixed time interval. The training sequence continues until all processors in the series have been trained in a similar manner. The input to the kth or last processor will comprise a set of input signals, the desired output responses to those input signals and the output of the (k-l)the processor. The input to each preceding processor will th separate sets of input signals which in one embodiment are the set of input signals to the kth processor, retrogressively, delayed in time by one additional time interval and the output of the previous processor. The system may be looked upon as a minimum entropy system in which the entropy or measure of uncertainty is decreased at each stage. When all of the processors have been trained, the system is ready for execution and the actual output of the last stage is a minimum entropy approximation of a proper desired output when an input signal, without a corresponding desired response, is introduced into the completed system of cascaded processors.

Abstract translation: 系统由级联的一系列可训练的非线性处理器组成。 处理器按如下顺序进行训练。 在该序列的第一阶段中，将包括系统要被训练的输入信息和对这些输入信号的对应的一组期望响应的一组输入信号引入第一处理器。 当第一处理器已经在整个集合上被训练时，第二阶段开始，其中第二组输入信号连同第一处理器的输出和对应的期望响应集合被引入第二处理器。 在该第二阶段期间，到第一和第二处理器的输入信号是顺序对应的。 在本发明的一个实施例中，到第一处理器的输入信号的集合包括被延迟固定时间间隔的相同的一组输入信号被引入第二处理器。