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    Expanded search method and system in trained processors
    2.
    发明授权
    Expanded search method and system in trained processors 失效
    培训处理器中扩展的搜索方法和系统

    公开(公告)号：US3596258A

    公开(公告)日：1971-07-27

    申请号：US3596258D

    申请日：1969-12-30

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： CHOATE WILLIAM C ,  MASTEN MICHAEL K

    IPC: G06F17/30 ,  G06F7/02

    CPC classification number: G06F17/30961

    Abstract: Operation of a trained processor beyond an untrained point where successive time sampled sets of level dependent signals stored in a tree storage array at successive memory locations along with a trained response for each set at a subsequent memory location form a data base to locate and extract a trained response to subsequent sets encountered following completion of training. A test set forming an untrained point is sequentially compared with each trained set stored in memory to establish and store a difference function relative to each trained set. Logic means selects as the trained response for the untrained point the trained response from those trained responses for which the trained sets have the same minimal difference function and which satisfies a predetermined decision criteria.

    Storage minimized optimum processor
    4.
    发明授权
    Storage minimized optimum processor 失效
    存储最小化最优处理器

    公开(公告)号：US3678470A

    公开(公告)日：1972-07-18

    申请号：US3678470D

    申请日：1971-03-09

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： CHOATE WILLIAM C ,  MASTEN MICHAEL K

    IPC: G06F17/30 ,  G06F3/05

    CPC classification number: G06F17/30961

    Abstract: A trainable signal processor having at least one input signal u and one desired output signal z applied thereto during training and having at least one input signal u and one actual output signal x derived therefrom during execution is provided. From each member of the input sequence u(ti) a key Ki is generated. Ki may have only a finite number of values and is a single valued function of u. Corresponding to a specific value of the Ki generated during training a trained response is derived from samples of the desired output signal z measured at instances ti at which that value of Ki occurred and is maintained in a tree allocated file. The file thereby associates with each set of Ki values a trained response. Storage is provided for only those sets of Ki values which actually occurred during training, generally constituting a small fraction of those sets which may theoretically occur, particularly when the input is of multidimensional character. During execution the tree allocated file provides for efficient retrieval of the trained responses which are employed in determining the actual output signal of the processor.

    Abstract translation: 提供在训练期间具有至少一个输入信号u和一个期望的输出信号z的可训练信号处理器，并且在执行期间具有至少一个输入信号u和从其导出的一个实际输出信号x。 从输入序列u（ti）的每个成员生成密钥Ki。 Ki可能只有有限数量的值，并且是u的单值函数。 对应于在训练期间产生的Ki的特定值，从经验值Ki发生并保持在树分配文件中的实例ti处测量的期望输出信号z的样本导出经过训练的响应。 因此，文件将每个Ki值组合成训练有素的响应。 存储只提供训练期间实际发生的那些一组Ki值，通常构成理论上可以发生的那些集合的一小部分，特别是当输入是多维特征时。 在执行期间，分配树的文件提供用于确定处理器的实际输出信号所采用的经过训练的响应的有效检索。

    Trainable entropy system
    6.
    发明授权
    Trainable entropy system 失效
    可培训入门系统

    公开(公告)号：US3702986A

    公开(公告)日：1972-11-14

    申请号：US3702986D

    申请日：1970-07-06

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： TAYLOR FREDRICK JAMES ,  CHOATE WILLIAM C

    IPC: G06F15/18

    CPC classification number: G06N99/005

    Abstract: A system is comprised of a series of trainable nonlinear processors in cascade. The processors are trained in sequence as follows. In a first phase of the sequence, a set of input signals comprising input information upon which the system is to be trained and a corresponding set of desired responses to these input signals are introduced into the first processor. When the first processor has been trained over the entire set, a second phase commences in which a second set of input signals along with the output of the first processor and corresponding set of desired responses are introduced into the second processor. During this second phase the input signals to the first and second processors are in sequential correspondence. In one embodiment of the invention the set of input signals to the first processor comprises the same set of input signals being introduced into the second processor delayed by a fixed time interval. The training sequence continues until all processors in the series have been trained in a similar manner. The input to the kth or last processor will comprise a set of input signals, the desired output responses to those input signals and the output of the (k-l)the processor. The input to each preceding processor will th separate sets of input signals which in one embodiment are the set of input signals to the kth processor, retrogressively, delayed in time by one additional time interval and the output of the previous processor. The system may be looked upon as a minimum entropy system in which the entropy or measure of uncertainty is decreased at each stage. When all of the processors have been trained, the system is ready for execution and the actual output of the last stage is a minimum entropy approximation of a proper desired output when an input signal, without a corresponding desired response, is introduced into the completed system of cascaded processors.

    Abstract translation: 系统由级联的一系列可训练的非线性处理器组成。 处理器按如下顺序进行训练。 在该序列的第一阶段中，将包括系统要被训练的输入信息和对这些输入信号的对应的一组期望响应的一组输入信号引入第一处理器。 当第一处理器已经在整个集合上被训练时，第二阶段开始，其中第二组输入信号连同第一处理器的输出和对应的期望响应集合被引入第二处理器。 在该第二阶段期间，到第一和第二处理器的输入信号是顺序对应的。 在本发明的一个实施例中，到第一处理器的输入信号的集合包括被延迟固定时间间隔的相同的一组输入信号被引入第二处理器。

    Expanded search for tree allocated processors
    7.
    发明授权
    Expanded search for tree allocated processors 失效
    扩展搜索树分配处理器

    公开(公告)号：US3678461A

    公开(公告)日：1972-07-18

    申请号：US3678461D

    申请日：1970-06-01

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： CHOATE WILLIAM C ,  MASTEN MICHAEL K

    IPC: G06F17/30 ,  G06K9/68 ,  G06F15/40

    CPC classification number: G06K9/68 ,  Y10S707/99933

    Abstract: A trained processor is described which operates beyond an untrained point. Information is stored in a memory array in a tree allocated file. Information is stored in the memory as key functions with associated trained responses. After the processor has been trained, it is able during an execution cycle to find and appropriate response for other key functions. These key functions are compared with the reference key functions stored in the memory array to find an appropriate trained response. During the execution cycle, there are some key functions for which there is no corresponding reference key function stored in the memory array and thereupon no appropriate trained response. These key functions for which no trained response is found are termed untrained points. Thereupon a key function which constitutes an untrained point is effectively compared with the reference key functions stored in the memory array to establish and store a difference function relative to each stored key function. Logic means then selects for the untrained point a trained response from those trained responses best satisfying a predetermined decision criteria. During the comparison operation, conditions are measured that indicate when key functions corresponding to a given group of trained responses cannot be an appropriate response for the untrained point in question. Logic means waive further examination of stored key functions, and thereby greatly expedite the efficiency of search.

    Abstract translation: 描述了经过训练的处理器，其操作超过未训练的点。 信息存储在树分配文件中的存储器阵列中。 信息作为具有相关训练响应的关键功能存储在存储器中。 处理器经过培训后，可以在执行周期中查找和适当响应其他主要功能。 将这些关键功能与存储在存储器阵列中的参考键功能进行比较，以找到适当的训练响应。 在执行周期中，存在一些关键功能，其中没有对应的参考键功能存储在存储器阵列中，因此没有适当的训练响应。 没有发现训练有素的反应的这些关键功能被称为未经训练的点。 因此，构成未经训练的点的关键功能与存储在存储器阵列中的参考键功能有效地进行比较，以建立和存储相对于每个存储的键功能的差分函数。 然后，逻辑手段为未训练的点选择经过训练的响应，该训练的响应最好地满足预定的判定标准。 在比较操作期间，测量条件，其指示对应于给定组训练的响应的关键功能何时不能是所讨论的未经训练的点的适当响应。 逻辑意味着放弃对存储的关键功能的进一步检查，从而大大加快搜索的效率。

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