Battery protector hibernate input separate from VDD, low power output

    公开(公告)号:US11139664B2

    公开(公告)日:2021-10-05

    申请号:US16127963

    申请日:2018-09-11

    Abstract: A battery protector includes analog frontend circuitry coupled to a hibernate mode input terminal that is one of configured to couple to a high voltage connector terminal when the system is connected to an external load or charger to define an active mode and configured to float when the system is disconnected from the external load or charger to define a hibernate mode. The analog frontend circuitry is configured to provide a signal at an output thereof to distinguish, in the absence of an external ground connection, between connected and floating conditions for the hibernate mode input terminal. Digital logic is coupled with the output of the analog frontend circuitry, the digital logic providing a digital signal to control whether the battery protector is operating in the active mode or the hibernate mode based on the signal at the output of the analog frontend circuitry.

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