公开(公告)号：US09401702B2

公开(公告)日：2016-07-26

申请号：US14250880

申请日：2014-04-11

Applicant: Texas Instruments Incorporated

Inventor： Aswin Srinivasa Rao ,  Anand Kudari ,  Karthik Subburaj

IPC: H03C1/00 ,  H03K7/06 ,  H04L27/12 ,  H04L27/10

CPC classification number: H03K7/06 ,  H04L27/10 ,  H04L27/12 ,  H04L27/127

Abstract: Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

Abstract translation: 通过选择高频时钟的适当相位来产生调制的中间时钟频率来实现二进制频移键控调制。 高频时钟选择为（M + 0.5）* fc，其中fc是载波频率，M是整数。 根据要发送的二进制数据'1'或'0'，来自高频时钟的“M”或“M + 1”个时钟相位被转换为比载波频率快2倍N倍的中间时钟， 其中N是整数。 该完全在数字域中产生的中间时钟在其中具有所需的数据调制，并用于产生以载波频率工作的N个脉宽调制（PWM）相位。 然后适当地称重N相，以合成基本上抑制其低次谐波的正弦波形。

公开(公告)号：US20150295569A1

公开(公告)日：2015-10-15

申请号：US14250880

申请日：2014-04-11

Applicant: Texas Instruments Incorporated

Inventor： Aswin Srinivasa Rao ,  Anand Kudari ,  Karthik Subburaj

IPC: H03K7/06

CPC classification number: H03K7/06 ,  H04L27/10 ,  H04L27/12 ,  H04L27/127

Abstract: Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

Abstract translation: 通过选择高频时钟的适当相位来产生调制中间时钟频率来实现二进制频移键控调制。 高频时钟选择为（M + 0.5）* fc，其中fc是载波频率，M是整数。 根据要发送的二进制数据'1'或'0'，来自高频时钟的“M”或“M + 1”个时钟相位被转换为比载波频率快2倍N倍的中间时钟， 其中N是整数。 该完全在数字域中产生的中间时钟在其中具有所需的数据调制，并用于产生以载波频率工作的N个脉宽调制（PWM）相位。 然后适当地称重N相，以合成基本上抑制其低次谐波的正弦波形。

公开(公告)号：US10671105B2

公开(公告)日：2020-06-02

申请号：US15913321

申请日：2018-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael James Mills ,  Anand Kudari ,  Timothy Bryan Merkin

IPC: G05F1/575 ,  G05F1/59

Abstract: An apparatus includes an amplifier configured to compare a feedback input, corresponding to a voltage of an output voltage node, with respect to a reference input and to provide a control output to control the output voltage node based on a difference between the feedback input and the reference input. At least two source circuits are coupled with the output voltage node. Each of the source circuits are configured to provide respective voltage sources to supply electrical power to the output voltage node.