公开(公告)号：US20200371793A1

公开(公告)日：2020-11-26

申请号：US16422602

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Asheesh BHARDWAJ ,  Dheera Balasubramanian SAMUDRALA ,  Timothy D. ANDERSON

IPC: G06F9/30 ,  G06F17/14

Abstract: A method to store source data in a processor in response to a bit-reversed vector store instruction includes specifying, in respective fields of the bit-reversed vector store instruction, a first source register containing the source data and a second source register containing address data. The first source register includes a plurality of lanes and each lane contains an initial data element having an associated index value. The method also includes executing the bit-reversed vector store instruction by creating reordered source data by, for each lane, replacing the initial data element in the lane with the data element having a bit-reversed index value relative to the associated index value of the initial data element; and storing the reordered source data in contiguous locations in a memory beginning at a location specified by the address data.

公开(公告)号：US20180349096A1

公开(公告)日：2018-12-06

申请号：US15995647

申请日：2018-06-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arthur John REDFERN ,  Asheesh BHARDWAJ ,  Tarek Aziz LAHLOU ,  William Franklin LEVEN

IPC: G06F7/36 ,  G06F9/30 ,  G06F7/24 ,  G06F7/32

Abstract: A merge sort accelerator (MSA) includes a pre-processing stage configured to receive an input vector and generate a pre-processing output vector based on a pre-processing instruction and the input vector. The MSA also includes a merge sort network having multiple sorting stages configured to be selectively enabled. The merge sort network is configured to receive the pre-processing output vector and generate a sorted output vector based on a sorting instruction and the pre-processing output vector. The MSA includes an accumulator stage configured to receive the sorted output vector and update an accumulator vector based on the accumulator instruction and the sorted output vector. The MSA also includes a post-processing stage configured to receive the accumulator vector and generate a post-processing output vector based on a post-processing instruction and the accumulator vector.