中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

30 records (took 0.02 seconds)

    IMPLIED FENCE ON STREAM OPEN
    1.
    发明申请
    IMPLIED FENCE ON STREAM OPEN 有权

    公开(公告)号：US20210216316A1

    公开(公告)日：2021-07-15

    申请号：US17216821

    申请日：2021-03-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naveen BHORIA ,  Kai CHIRCA ,  Timothy D. ANDERSON ,  Duc BUI ,  Abhijeet A. CHACHAD ,  Son Hung TRAN

    IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F11/10 ,  G06F9/345

    Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.

    VECTOR MAXIMUM AND MINIMUM WITH INDEXING
    2.
    发明申请
    VECTOR MAXIMUM AND MINIMUM WITH INDEXING 审中-公开

    公开(公告)号：US20200371788A1

    公开(公告)日：2020-11-26

    申请号：US16422501

    申请日：2019-05-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Duc BUI ,  Peter Richard DENT ,  Timothy D. ANDERSON

    IPC: G06F9/30

    Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

    VECTOR FLOATING-POINT SCALE
    3.
    发明申请
    VECTOR FLOATING-POINT SCALE 审中-公开

    公开(公告)号：US20200371784A1

    公开(公告)日：2020-11-26

    申请号：US16422754

    申请日：2019-05-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK

    IPC: G06F9/30

    Abstract: A method to scale source data in a processor in response to a vector floating-point scale instruction includes specifying a first source register containing the source data, a second source register containing scale values, and a destination register to store scaled source data. The first source register includes a plurality of lanes that each contains a floating-point value and the second source register and the destination register each includes a plurality of lanes corresponding to the lanes of the first source register. The method includes executing the vector floating-point scale instruction by, for each lane in the first source register adding the scale value in the corresponding lane of the second source register to an exponent field of the floating-point value in the lane of the first source register to create a scaled floating-point value, and storing the scaled floating-point value in the corresponding lane of the destination register.

    VARIABLE LATENCY INSTRUCTIONS
    5.
    发明申请
    VARIABLE LATENCY INSTRUCTIONS 有权

    公开(公告)号：US20240411559A1

    公开(公告)日：2024-12-12

    申请号：US18808167

    申请日：2024-08-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. ANDERSON

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0875 ,  G06F12/0897

    Abstract: Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.

    NESTED LOOP CONTROL
    6.
    发明公开
    NESTED LOOP CONTROL 审中-公开

    公开(公告)号：US20240281231A1

    公开(公告)日：2024-08-22

    申请号：US18648583

    申请日：2024-04-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai CHIRCA ,  Timothy D. ANDERSON ,  Todd T. HAHN ,  Alan L. DAVIS

    IPC: G06F8/41 ,  G06F5/06 ,  G06F9/30

    CPC classification number: G06F8/433 ,  G06F5/06 ,  G06F9/30065

    Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

    NESTED LOOP CONTROL
    8.
    发明申请
    NESTED LOOP CONTROL 审中-公开

    公开(公告)号：US20200371800A1

    公开(公告)日：2020-11-26

    申请号：US16422823

    申请日：2019-05-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai CHIRCA ,  Timothy D. ANDERSON ,  Todd T. HAHN ,  Alan L. DAVIS

    IPC: G06F9/30

    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

Patent Agency Ranking