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公开(公告)号：US10083374B2
公开(公告)日：2018-09-25
申请号：US15376473
申请日：2016-12-12
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Manu Mathew , Chaitanya Satish Ghone
CPC classification number: G06K9/4628 , G06K9/522 , G06K9/6271
Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.
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公开(公告)号：US20130272429A1
公开(公告)日：2013-10-17
申请号：US13864131
申请日：2013-04-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: H04N7/26
CPC classification number: H04N19/186 , H04N19/44
Abstract: Checksum computation for video coding is provided that breaks the dependency between the color components of a picture in the prior art. More specifically, rather than computing a single checksum for a picture as in the prior art, a separate checksum is computed for each color component. Computing a separate checksum for each color component enables parallel computation of the component checksums. Methods are provided for computing three separate checksums after a picture is decoded. Methods are also provided for computing three separate checksums on a largest coding unit basis, thus allowing the checksums for a picture to be computed as the picture is being decoded.
Abstract translation: 提供了用于视频编码的校验和计算，其破坏了现有技术中的图像的颜色分量之间的依赖关系。 更具体地说，与现有技术相比，不是计算图像的单个校验和，而是为每个颜色分量计算单独的校验和。 为每个颜色组件计算单独的校验和，可以并行计算组件校验和。 提供了在解码图片之后计算三个单独的校验和的方法。 还提供了用于在最大编码单元的基础上计算三个单独的校验和的方法，从而允许当图像被解码时计算图像的校验和。
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公开(公告)号：US09906815B2
公开(公告)日：2018-02-27
申请号：US13671344
申请日：2012-11-07
Applicant: Texas Instruments Incorporated
IPC: H04N7/32 , H04N19/895 , H04N19/172 , H04N19/107 , H04N19/39 , H04N19/65
CPC classification number: H04N19/895 , H04N19/107 , H04N19/172 , H04N19/39 , H04N19/65
Abstract: A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture.
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公开(公告)号：US20150296212A1
公开(公告)日：2015-10-15
申请号：US14684334
申请日：2015-04-11
Applicant: Texas Instruments Incorporated
Inventor： Dipan Kumar Mandal , Mihir Narendra Mody , Mahesh Madhukar Mehendale , Chaitanya Satish Ghone , Piyali Goswami , Naresh Kumar Yadav , Hetul Sanghvi , Niraj Nandan
IPC: H04N19/42 , G06F9/30 , H04N19/463 , G06F9/38
CPC classification number: H04N19/42 , G06F9/30181 , G06F9/3885 , H04N19/43 , H04N19/463
Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.
Abstract translation: 提供了一种用于视频编码解码引擎的控制处理器，其包括指令流水线。 指令流水线包括与指令存储器耦合以取指令的指令提取级，耦合到指令提取级以接收所取指令的指令解码级，以及耦合到指令解码级的接收和执行解码指令的执行级。 指令解码级和指令执行级被配置为解码和执行专门用于加速视频序列编码和编码视频位流解码的控制处理器的指令集中的一组指令。
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公开(公告)号：US12167049B2
公开(公告)日：2024-12-10
申请号：US18197177
申请日：2023-05-15
Applicant: Texas Instruments Incorporated
IPC: H04N19/895 , H04N19/107 , H04N19/172 , H04N19/39 , H04N19/65
Abstract: A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture.
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Patent Agency Ranking
公开(公告)号：US20230283808A1
公开(公告)日：2023-09-07
申请号：US18197177
申请日：2023-05-15
Applicant: Texas Instruments Incorporated
IPC: H04N19/895 , H04N19/172 , H04N19/107 , H04N19/39 , H04N19/65
CPC classification number: H04N19/895 , H04N19/172 , H04N19/107 , H04N19/39 , H04N19/65
Abstract: A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture.
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公开(公告)号：US20180184130A1
公开(公告)日：2018-06-28
申请号：US15905588
申请日：2018-02-26
Applicant: Texas Instruments Incorporated
IPC: H04N19/895 , H04N19/65 , H04N19/39 , H04N19/107 , H04N19/172
CPC classification number: H04N19/895 , H04N19/107 , H04N19/172 , H04N19/39 , H04N19/65
Abstract: A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture.
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公开(公告)号：US20180165543A1
公开(公告)日：2018-06-14
申请号：US15376473
申请日：2016-12-12
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Manu Mathew , Chaitanya Satish Ghone
CPC classification number: G06K9/6245 , G06K9/4652
Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.
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公开(公告)号：US10397591B2
公开(公告)日：2019-08-27
申请号：US14684334
申请日：2015-04-11
Applicant: Texas Instruments Incorporated
Inventor： Dipan Kumar Mandal , Mihir Narendra Mody , Mahesh Madhukar Mehendale , Chaitanya Satish Ghone , Piyali Goswami , Naresh Kumar Yadav , Hetul Sanghvi , Niraj Nandan
IPC: H04N19/43 , H04N19/42 , H04N19/463 , G06F9/38
Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.
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公开(公告)号：US20180357513A1
公开(公告)日：2018-12-13
申请号：US16108237
申请日：2018-08-22
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Manu Mathew , Chaitanya Satish Ghone
CPC classification number: G06K9/4628 , G06K9/522 , G06K9/6271
Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.
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