公开(公告)号：US20250028831A1

公开(公告)日：2025-01-23

申请号：US18882164

申请日：2024-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Uri WEINRIB ,  Barak CHERCHES ,  Clive David BITTLESTONE

IPC: G06F21/56 ,  G06F21/52

Abstract: A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.

公开(公告)号：US20230214490A1

公开(公告)日：2023-07-06

申请号：US17853612

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Uri WEINRIB ,  Barak CHERCHES ,  Clive David BITTLESTONE

IPC: G06F21/56 ,  G06F21/52

CPC classification number: G06F21/566 ,  G06F21/52 ,  G06F2221/034

Abstract: A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.