公开(公告)号：US10191097B2

公开(公告)日：2019-01-29

申请号：US15389053

申请日：2016-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Charles Kasimer Sestok, IV ,  Srinath Ramaswamy ,  Anand Ganesh Dabak ,  Domingo G. Garcia ,  Baher Haroun ,  Alan Henry Leek ,  Ryan Michael Brown

IPC: G01R27/16

Abstract: A microcontroller-based system for measuring the impedance of a device under test (DUT), responsive to a square wave stimulus, includes parallel stimulus signal paths, selectable by a switch, that can correspond to different stimulus frequency ranges. At least one of the paths includes an off-chip PLL and integer divider circuit to modify the frequency of the stimulus. A discrete Fourier transform executed by a processor is used to determine the impedance of the DUT at the stimulus frequency. Multiple frequencies can be analyzed at the same time by using a summation circuit and/or by analyzing odd harmonics of the stimulus frequency.

公开(公告)号：US09429645B2

公开(公告)日：2016-08-30

申请号：US14684777

申请日：2015-04-13

Applicant: Texas Instruments Incorporated

Inventor： Domingo G. Garcia ,  Mohamed Mansour ,  Murtaza Ali

IPC: G01S7/00 ,  G01S7/52 ,  G06F17/14

CPC classification number: G01S7/52 ,  G06F17/148

Abstract: An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to the demultiplexer. A first multiplexer is coupled to each of the sample buffers. A filter is coupled to the first multiplexer. A bypass delay circuit is coupled to the first multiplexer, and a second multiplexer is coupled to the filter and the bypass delay circuit.

公开(公告)号：US20150219754A1

公开(公告)日：2015-08-06

申请号：US14684777

申请日：2015-04-13

Applicant: Texas Instruments Incorporated

Inventor： Domingo G. Garcia ,  Mohamed Mansour ,  Murtaza Ali

IPC: G01S7/52

CPC classification number: G01S7/52 ,  G06F17/148

Abstract: An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to the demultiplexer. A first multiplexer is coupled to each of the sample buffers. A filter is coupled to the first multiplexer. A bypass delay circuit is coupled to the first multiplexer, and a second multiplexer is coupled to the filter and the bypass delay circuit.

Abstract translation: 提供了一种装置。 在该装置中，解复用器被配置为接收输入信号，并且多个采样缓冲器中的每一个被耦合到解复用器。 第一多路复用器耦合到每个采样缓冲器。 滤波器耦合到第一多路复用器。 旁路延迟电路耦合到第一多路复用器，并且第二多路复用器耦合到滤波器和旁路延迟电路。