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公开(公告)号：US10651836B1
公开(公告)日：2020-05-12
申请号：US16281622
申请日：2019-02-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A clock generator circuit includes a clock divider circuit, a clock pulse control circuit, a phase shifter circuit, and a clock multiplexer circuit. The clock divider circuit is configured to generate a divided clock having a frequency that is a programmable fraction of a frequency of an input clock. The clock pulse control circuit is coupled to the clock divider circuit, and is configured to generate a pulse shaped clock that includes a clock burst comprising a programmable number of adjacent cycles of the divided clock. The phase shifter circuit is coupled to the clock control circuit, and is configured to generate a plurality of phase shifted clocks. Each of phase shifted clocks is a differently delayed version of the pulse shaped clock. The clock multiplexer circuit is coupled to the phase shifter circuit, and is configured to selectively route each of the phase shifted clocks to an output terminal.
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公开(公告)号：US11204385B2
公开(公告)日：2021-12-21
申请号：US16863906
申请日：2020-04-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G01R31/3177 , G06F1/08
Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.
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