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公开(公告)号：US11204385B2
公开(公告)日：2021-12-21
申请号：US16863906
申请日：2020-04-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G01R31/3177 , G06F1/08
Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.
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公开(公告)号：US11095485B2
公开(公告)日：2021-08-17
申请号：US16695586
申请日：2019-11-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Sashidharan Venkatraman , Sundarrajan Rangachari , Sarma Sundareswara Gunturi , Sthanunathan Ramakrishnan
Abstract: An electrical system includes a transceiver with an IQ estimator and an IQ mismatch corrector. The electrical system also includes an antenna coupled to the transceiver. The IQ estimator is configured to perform frequency-domain IQ mismatch analysis to determine an IQ mismatch estimate at available frequency bins of a baseband data signal. The IQ mismatch corrector is configured to correct the baseband data signal based on the IQ mismatch estimate.
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公开(公告)号：US20210148976A1
公开(公告)日：2021-05-20
申请号：US17160461
申请日：2021-01-28
Applicant: Texas Instruments Incorporated
Inventor： Sundarrajan Rangachari , Saket Jalan
IPC: G01R31/319 , G01R31/317 , G01R31/3177
Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.
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公开(公告)号：US20210083695A1
公开(公告)日：2021-03-18
申请号：US17022871
申请日：2020-09-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh Balakrishnan , Sriram Murali , Sundarrajan Rangachari , Yeswanth Guntupalli
IPC: H04B1/00
Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sinc response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sinc filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.
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公开(公告)号：US10396829B2
公开(公告)日：2019-08-27
申请号：US16110478
申请日：2018-08-23
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh Balakrishnan , Suvam Nandi , Sundarrajan Rangachari
Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
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Patent Agency Ranking
公开(公告)号：US09491012B1
公开(公告)日：2016-11-08
申请号：US14745349
申请日：2015-06-19
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh Balakrishnan , Sriram Murali , Sundarrajan Rangachari , Sarma Sundareswara Gunturi
CPC classification number: H04L25/03859 , H03F1/3241 , H04B1/04 , H04B1/0475 , H04B2001/0425
Abstract: Example embodiments of systems and methods of direct oversampled low PAR pulse shaping encapsulating DSSS spreading are disclosed herein. Pulse-shaping of a DSSS spread data symbol stream results in a small number of waveform patterns to choose from for any data-symbol window. Low complexity programmable look-up table (LUT) based direct pulse shaping may be implemented, while only needing to compute a negation function. The chosen pulse shape may generate a low PAR for the baseband signal, allowing for a reduction in the saturation power of the power amplifier, thereby reducing the overall transmitter power consumption.
Abstract translation: 本文公开了封装DSSS扩展的直接过采样低PAR脉冲整形的系统和方法的示例实施例。 DSSS扩展数据符号流的脉冲整形导致少量波形图案，可供任何数据符号窗口选择。 可以实现基于直接脉冲整形的低复杂度可编程查找表（LUT），而仅需要计算否定函数。 所选择的脉冲形状可以产生用于基带信号的低PAR，允许降低功率放大器的饱和功率，从而降低总的发射机功率消耗。
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公开(公告)号：US12160259B2
公开(公告)日：2024-12-03
申请号：US17544795
申请日：2021-12-07
Applicant: Texas Instruments Incorporated
Inventor： Sundarrajan Rangachari , Nagalinga Swamy Basayya Aremallapur , Kalyan Gudipati , Divyeshkumar Mahendrabhai Patel , Venkateshwara Reddy Pothapu , Aravind Vijayakumar , Sarma Sundareswara Gunturi , Jaiganesh Balakrishnan
Abstract: A technique for reinitializing a coupled circuit, the technique including receiving a common configuration value associated with states of a coupled circuit, tracking states associated with the coupled circuit while the coupled circuit is in a low power state based on the common configuration value, receiving the tracked state associated with the coupled circuit, receiving a scaling value associated with the coupled circuit, determining a current state of the coupled circuit based on the tracked state and the scaling value, and transmitting an indication of the current state to the coupled circuit when the coupled circuit has exited the low power state.
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公开(公告)号：US11320488B2
公开(公告)日：2022-05-03
申请号：US17160461
申请日：2021-01-28
Applicant: Texas Instruments Incorporated
Inventor： Sundarrajan Rangachari , Saket Jalan
IPC: G01R31/319 , G01R31/317 , G01R31/3177
Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.
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公开(公告)号：US11300615B2
公开(公告)日：2022-04-12
申请号：US16220209
申请日：2018-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prakash Narayanan , Sundarrajan Rangachari , Prashanth Saraf
IPC: G01R31/3183 , G01R31/3185 , G01R31/3181 , G01R31/317
Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.
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公开(公告)号：US10090866B2
公开(公告)日：2018-10-02
申请号：US15395135
申请日：2016-12-30
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh Balakrishnan , Suvam Nandi , Sundarrajan Rangachari
Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
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