公开(公告)号：US12223101B2

公开(公告)日：2025-02-11

申请号：US18376928

申请日：2023-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Allen North ,  Per Torstein Roine ,  Eric Thierry Jean Peeters

IPC: G06F21/85 ,  G06F13/28 ,  G06F15/78

Abstract: A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

公开(公告)号：US11783097B2

公开(公告)日：2023-10-10

申请号：US17962627

申请日：2022-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Allen North ,  Per Torstein Roine ,  Eric Thierry Jean Peeters

IPC: G06F21/85 ,  G06F13/28 ,  G06F15/78

CPC classification number: G06F21/85 ,  G06F13/287 ,  G06F15/7807

Abstract: A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

公开(公告)号：US10536441B2

公开(公告)日：2020-01-14

申请号：US15244208

申请日：2016-08-23

Applicant: Texas Instruments Incorporated

Inventor： Eric Thierry Peeters ,  Gregory Allen North

IPC: G06F21/74 ,  H04L29/06

Abstract: An embedded processor with a cryptographic co-processor operating in a multithreading environment, with inter-thread security for cryptography operations. A secure memory block accessible by the co-processor stores a plurality of key entries, each key entry storing data corresponding to a cryptography key, and a thread owner field that identifies an execution thread is associated with that key. A central processing unit issues a call to the co-processor to execute a cryptography operation along with a key identifier for the key to be used, and a thread identifier indicating the current execution thread. The co-processor compares the thread identifier received from the CPU with the thread owner field of the key entry corresponding to the key identifier. If the thread identifier matches the thread owner in the key entry, the key is retrieved from the secure memory block for use by the co-processor for the cryptography operation.

公开(公告)号：US11468202B2

公开(公告)日：2022-10-11

申请号：US17122234

申请日：2020-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Allen North ,  Per Torstein Roine ,  Eric Thierry Jean Peeters

IPC: G06F21/85 ,  G06F13/28 ,  G06F15/78

Abstract: A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit hays a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

公开(公告)号：US20190051812A1

公开(公告)日：2019-02-14

申请号：US15671252

申请日：2017-08-08

Applicant: Texas Instruments Incorporated

Inventor： Wei-Yan Shih ,  Sudhanshu Khanna ,  Michael Zwerg ,  Juergen Luebbe ,  Gregory Allen North ,  Steven C. Bartling ,  Leah Trautmann ,  Scott Robert Summerfelt

IPC: H01L41/107 ,  B06B1/06 ,  H01L41/04 ,  H01L41/047

Abstract: A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.

公开(公告)号：US20180063100A1

公开(公告)日：2018-03-01

申请号：US15244208

申请日：2016-08-23

Applicant: Texas Instruments Incorporated

Inventor： Eric Thierry Peeters ,  Gregory Allen North

IPC: H04L29/06

Abstract: An embedded processor with a cryptographic co-processor operating in a multithreading environment, with inter-thread security for cryptography operations. A secure memory block accessible by the co-processor stores a plurality of key entries, each key entry storing data corresponding to a cryptography key, and a thread owner field that identifies an execution thread is associated with that key. A central processing unit issues a call to the co-processor to execute a cryptography operation along with a key identifier for the key to be used, and a thread identifier indicating the current execution thread. The co-processor compares the thread identifier received from the CPU with the thread owner field of the key entry corresponding to the key identifier. If the thread identifier matches the thread owner in the key entry, the key is retrieved from the secure memory block for use by the co-processor for the cryptography operation.