Vector table load instruction with address generation field to access table offset value

    公开(公告)号:US11468003B2

    公开(公告)日:2022-10-11

    申请号:US17026412

    申请日:2020-09-21

    Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

    PROCESSOR WITH TABLE LOOKUP UNIT
    2.
    发明申请

    公开(公告)号:US20230049454A1

    公开(公告)日:2023-02-16

    申请号:US17962585

    申请日:2022-10-10

    Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

    PROCESSOR WITH TABLE LOOKUP UNIT
    3.
    发明申请

    公开(公告)号:US20210004349A1

    公开(公告)日:2021-01-07

    申请号:US17026412

    申请日:2020-09-21

    Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

    Vector processor calculation of local binary patterns
    4.
    发明授权
    Vector processor calculation of local binary patterns 有权
    矢量处理器计算局部二进制模式

    公开(公告)号:US09336454B2

    公开(公告)日:2016-05-10

    申请号:US13921778

    申请日:2013-06-19

    CPC classification number: G06K9/4604 G06K2009/4666

    Abstract: A method (and system) of determining a local binary pattern in an image includes selecting an orientation. For each pixel in the image, the method further includes determining a binary decision for each such pixel relative to one neighboring pixel of the orientation, selecting a new orientation, and repeating the determination of the binary decision for each pixel in the image relative to one neighboring pixel of the newly selected orientation.

    Abstract translation: 确定图像中的局部二进制图案的方法(和系统)包括选择取向。 对于图像中的每个像素,所述方法还包括针对所述方向的一个相邻像素确定每个所述像素的二进制判定,选择新的取向,以及重复所述图像中每个像素相对于一个的所述二进制决定的确定 新选择的方位的相邻像素。

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