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公开(公告)号：US11128390B1
公开(公告)日：2021-09-21
申请号：US16929352
申请日：2020-07-15
Applicant: Texas Instruments Incorporated
Inventor： Kiran Rajmohan , Kalyan Chakravarthi Chekuri
Abstract: A test system and interface circuitry for antenna-free bit error rate testing of an electronic device under test, including a pulse shaping circuit with a pulse shaping filter circuit to pulse shape a modulating signal before amplitude modulation with a carrier signal, and the amplitude modulated signal is coupled directly or via a transformer and a socket to the device under test without antennas to facilitate automated device testing with simple reconfiguration of signal generators for different device type. A method includes filtering a square wave modulating signal to create a pulse shaped modulating signal, amplitude modulating a carrier signal with the pulse shaped modulating signal to create an amplitude modulated signal, providing the amplitude modulated signal to the socket, and evaluating a bit error rate of the DUT according to receive data from the DUT and according to the BER test transmit data.
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公开(公告)号：US11994559B2
公开(公告)日：2024-05-28
申请号：US17871205
申请日：2022-07-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Lakshmanan Balasubramanian , Rubin Parekhji , Kalyan Chakravarthi Chekuri , Swathi G
IPC: G01R31/3183 , G06F30/30
CPC classification number: G01R31/31835 , G01R31/318307 , G01R31/318357 , G06F30/30
Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.
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公开(公告)号：US20230143500A1
公开(公告)日：2023-05-11
申请号：US17871205
申请日：2022-07-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Lakshmanan Balasubramanian , Rubin Parekhji , Kalyan Chakravarthi Chekuri , Swathi G
IPC: G01R31/3183
CPC classification number: G01R31/31835 , G01R31/318307 , G01R31/318357
Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.
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