公开(公告)号：US20230143500A1

公开(公告)日：2023-05-11

申请号：US17871205

申请日：2022-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Rubin Parekhji ,  Kalyan Chakravarthi Chekuri ,  Swathi G

IPC: G01R31/3183

CPC classification number: G01R31/31835 ,  G01R31/318307 ,  G01R31/318357

Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.

公开(公告)号：US11994559B2

公开(公告)日：2024-05-28

申请号：US17871205

申请日：2022-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Rubin Parekhji ,  Kalyan Chakravarthi Chekuri ,  Swathi G

IPC: G01R31/3183 ,  G06F30/30

CPC classification number: G01R31/31835 ,  G01R31/318307 ,  G01R31/318357 ,  G06F30/30

Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.

公开(公告)号：US20250165688A1

公开(公告)日：2025-05-22

申请号：US18513070

申请日：2023-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Rubin Parekhji ,  Supraja Ramakrishnan

IPC: G06F30/3308 ,  G06F119/02

Abstract: A method comprises creating an electronic circuit design having a plurality of electronic components, defining a fault condition imposable during a simulation of the electronic circuit design, and generating a simulation model based on the electronic circuit design. The method also comprises generating a simulation fault model representing the fault condition and executing a simulation of the simulation model to simulate operation of the electronic circuit design. During the execution of the simulation, the method comprises controlling the simulation fault model to begin an imposition of the fault condition within the simulation model, simulating circuit behavior of the simulation model in response to the imposition of the fault condition, controlling the simulation fault model to cease the imposition of the fault condition within the simulation model, and simulating circuit behavior of the simulation model in response to the cessation of the imposition of the fault condition.