公开(公告)号：US20200381342A1

公开(公告)日：2020-12-03

申请号：US16886130

申请日：2020-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： YongSeok PARK ,  Makarand Ramkrishna KULKARNI ,  Ricky Alan JACKSON ,  Byron Lovell WILLIAMS ,  Thomas Dyer BONIFIELD

IPC: H01L23/495 ,  H01L23/528 ,  H01L23/31 ,  H01L43/06 ,  G01R15/20 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: In examples, a semiconductor package comprises a first conductive terminal; a second conductive terminal; a conductive pathway coupling the first and second conductive terminals, the conductive pathway configured to generate a magnetic field; a semiconductor die including a circuit configured to detect the magnetic field; and first and second polyimide layers positioned between the conductive pathway and the semiconductor die.

公开(公告)号：US20240047330A1

公开(公告)日：2024-02-08

申请号：US18484310

申请日：2023-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Makarand Ramkrishna KULKARNI ,  Osvaldo Jorge LOPEZ ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Liang WAN

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49844 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L24/13

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US20220181241A1

公开(公告)日：2022-06-09

申请号：US17334491

申请日：2021-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Makarand Ramkrishna KULKARNI ,  Osvaldo Jorge LOPEZ ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Liang WAN

IPC: H01L23/498

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.