METHODS AND APPARATUS TO IMPLEMENT CURRENT LIMIT TEST MODE

    公开(公告)号:US20210234540A1

    公开(公告)日:2021-07-29

    申请号:US17228981

    申请日:2021-04-13

    Inventor: Pavol Balaz

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

    Methods and apparatus to implement current limit test mode

    公开(公告)号:US11095282B2

    公开(公告)日:2021-08-17

    申请号:US16670720

    申请日:2019-10-31

    Inventor: Pavol Balaz

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

    Closed loop commutation control for a switching power converter

    公开(公告)号:US12081118B2

    公开(公告)日:2024-09-03

    申请号:US18191916

    申请日:2023-03-29

    Inventor: Pavol Balaz

    CPC classification number: H02M1/44 H02M1/08

    Abstract: A system includes a switching power converter, including a first transistor having a first gate, a first drain, and a first source, the first drain adapted to be coupled to a power supply. The switching power converter also includes a second transistor having a second gate, a second drain, and a second source, the second gate coupled to a second gate driver, the second source adapted to be coupled to ground, and the second drain coupled to the first source. The switching power converter also includes a third transistor having a third gate, a third drain, and a third source, the third gate adapted to be coupled to a current source, the third source coupled to a resistor, and the third drain coupled to the first gate. The switching power converter includes a capacitor coupled to the first drain and adapted to be coupled to the current source.

    Methods and apparatus to implement current limit test mode

    公开(公告)号:US11757441B2

    公开(公告)日:2023-09-12

    申请号:US17228981

    申请日:2021-04-13

    Inventor: Pavol Balaz

    CPC classification number: H03K17/08122 H02M3/07 H03K2217/0063

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

    MULTI-CAPACITOR BOOTSTRAP CIRCUIT

    公开(公告)号:US20210328508A1

    公开(公告)日:2021-10-21

    申请号:US17361852

    申请日:2021-06-29

    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

    METHODS AND APPARATUS TO IMPLEMENT CURRENT LIMIT TEST MODE

    公开(公告)号:US20200186142A1

    公开(公告)日:2020-06-11

    申请号:US16670720

    申请日:2019-10-31

    Inventor: Pavol Balaz

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

    POWER-ON POP REDUCTION IN AUDIO SYSTEMS

    公开(公告)号:US20250048028A1

    公开(公告)日:2025-02-06

    申请号:US18362265

    申请日:2023-07-31

    Abstract: An apparatus includes a first power stage circuit having a first output and a power terminal, and a second power stage circuit having a second output and the power terminal. The apparatus further includes a control circuit having a control input, a first control output, and a second control output. In an example, the control input is coupled to the power terminal, the first control output is coupled to the first output, and the second control output is coupled to the second output. In an example, the control circuit is configured to, responsive to a first voltage at the power terminal being below a threshold voltage, set the first and second outputs to a second voltage.

    Methods and apparatus to implement current limit test mode

    公开(公告)号:US12107570B2

    公开(公告)日:2024-10-01

    申请号:US18359925

    申请日:2023-07-27

    Inventor: Pavol Balaz

    CPC classification number: H03K17/08122 H02M3/07 H03K2217/0063

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

    METHODS AND APPARATUS TO IMPLEMENT CURRENT LIMIT TEST MODE

    公开(公告)号:US20240022240A1

    公开(公告)日:2024-01-18

    申请号:US18359925

    申请日:2023-07-27

    Inventor: Pavol Balaz

    CPC classification number: H03K17/08122 H03K2217/0063 H02M3/07

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

    Closed loop commutation control for a switching power converter

    公开(公告)号:US11641158B2

    公开(公告)日:2023-05-02

    申请号:US17193724

    申请日:2021-03-05

    Inventor: Pavol Balaz

    Abstract: A system includes a switching power converter, including a first transistor having a first gate, a first drain, and a first source, the first drain adapted to be coupled to a power supply. The switching power converter also includes a second transistor having a second gate, a second drain, and a second source, the second gate coupled to a second gate driver, the second source adapted to be coupled to ground, and the second drain coupled to the first source. The switching power converter also includes a third transistor having a third gate, a third drain, and a third source, the third gate adapted to be coupled to a current source, the third source coupled to a resistor, and the third drain coupled to the first gate. The switching power converter includes a capacitor coupled to the first drain and adapted to be coupled to the current source.

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