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公开(公告)号：US20210310996A1
公开(公告)日：2021-10-07
申请号：US17350552
申请日：2021-06-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prashuk JAIN , Ravikumar PATTIPAKA , Vajeed Nimran PARAMBIL ABDUL RAHEEM , Sandeep Kesrimal OSWAL
Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
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Patent Agency Ranking
公开(公告)号：US20240291451A1
公开(公告)日：2024-08-29
申请号：US18175785
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ravikumar PATTIPAKA , Raja SEKHAR , Sandeep Kesrimal OSWAL
CPC classification number: H03F3/45076 , H03F1/26 , H03F3/211
Abstract: In an example, a circuit includes a high side output transistor having a control terminal coupled to a first capacitor, and includes a low side output transistor having a control terminal coupled to a second capacitor and a balancing capacitor. The circuit includes a first differential input stage configured to receive a differential input and provide a first output current to the control terminal of the high side output transistor. The circuit includes a second differential input stage configured to receive the differential input and provide a second output current to the control terminal of the low side output transistor. The circuit includes a floating battery coupled to the control terminal of the high side output transistor and the control terminal of the low side output transistor. The balancing capacitor balances a gate-to-source capacitance of the low side output transistor with a gate-to-source capacitance of the high side output transistor.
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3.发明申请公开(公告)号：US20200212954A1
公开(公告)日：2020-07-02
申请号：US16234672
申请日：2018-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aravind MIRIYALA , Ravikumar PATTIPAKA , Raja Sekhar KANAKAMEDALA , Sandeep Kesrimal OSWAL
Abstract: An ultrasound system includes a transmit-receive switch. The transmit-receive switch includes a combined transmit-receive and return-to-zero (RTZ) path. The combined transmit-receive and RTZ path includes a transistor with a first current terminal, a second current terminal, and a control terminal. The second current terminal of the transistor is coupled to a ground node via a first switch and is coupled to a receive node via a second switch. The ultrasound system also includes a receiver front-end circuit coupled to the receive node.
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公开(公告)号：US20240223164A1
公开(公告)日：2024-07-04
申请号：US18496465
申请日：2023-10-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ketan SHARMA , Ravikumar PATTIPAKA , Vajeed NIMRAN , Aravind MIRIYALA , Shabbir AMJHERA WALA , Savyan KANISSERRY
IPC: H03K3/021 , H03K3/3568
CPC classification number: H03K3/021 , H03K3/3568
Abstract: In some examples, a pulser circuit is configured to provide a pulse signal in a first operational state, pre-charge components of the pulser circuit via a first signal path in a second operational state following the first operational state, wherein the first signal path includes first components having a first voltage tolerance and second components having a second voltage tolerance, the first voltage tolerance being less than the second voltage tolerance, and discharge a voltage of the pulser circuit to ground in a third operational state between the first operational state and the second operational state, and following the second operational state.
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5.发明公开公开(公告)号：US20240120962A1
公开(公告)日：2024-04-11
申请号：US18543305
申请日：2023-12-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aravind MIRIYALA , Ravikumar PATTIPAKA , Raja Sekhar KANAKAMEDALA , Sandeep Kesrimal OSWAL
Abstract: An ultrasound system includes a transmit-receive switch. The transmit-receive switch includes a combined transmit-receive and return-to-zero (RTZ) path. The combined transmit-receive and RTZ path includes a transistor with a first current terminal, a second current terminal, and a control terminal. The second current terminal of the transistor is coupled to a ground node via a first switch and is coupled to a receive node via a second switch. The ultrasound system also includes a receiver front-end circuit coupled to the receive node.
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公开(公告)号：US20180137853A1
公开(公告)日：2018-05-17
申请号：US15782945
申请日：2017-10-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ravikumar PATTIPAKA , Vajeed NIMRAN , Sandeep OSWAL
CPC classification number: G10K11/34 , A61B8/4494 , A61B8/461 , A61B8/488 , G01S7/52046 , G01S15/8915 , G10K11/346
Abstract: A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.
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