公开(公告)号：US20150287647A1

公开(公告)日：2015-10-08

申请号：US14746106

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean RILEY ,  Seung-Chul SONG

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

公开(公告)号：US20150311304A1

公开(公告)日：2015-10-29

申请号：US14740431

申请日：2015-06-16

Applicant: Texas Instruments Incorporated

Inventor： Chet Vernon LENOX ,  Seung-Chul SONG ,  Brian K. KIRKPATRICK

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

公开(公告)号：US20160254197A1

公开(公告)日：2016-09-01

申请号：US15148497

申请日：2016-05-06

Applicant: Texas Instruments Incorporated

Inventor： Chet Vernon LENOX ,  Seung-Chul SONG ,  Brian K. KIRKPATRICK

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

公开(公告)号：US20150279966A1

公开(公告)日：2015-10-01

申请号：US14740438

申请日：2015-06-16

Applicant: Texas Instruments Incorporated

Inventor： Chet Vernon LENOX ,  Seung-Chul SONG ,  Brian K. KIRKPATRICK

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

公开(公告)号：US20150069516A1

公开(公告)日：2015-03-12

申请号：US14022317

申请日：2013-09-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chet Vernon LENOX ,  Seung-Chul SONG ,  Brian K. Kirkpatrick

IPC: H01L21/8234 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

Abstract translation: 通过去除牺牲栅极电介质层和牺牲栅极以形成栅极腔来形成集成电路。 在栅腔中形成保形电介质第一衬垫，并且在第一衬垫上形成共形第二衬垫。 第一蚀刻从栅极腔的底部去除第二衬垫，使第二衬垫的材料留在栅腔的侧壁上。 第二蚀刻从第二衬垫暴露的栅腔的底部去除第一衬垫，在栅腔的侧壁上的第二衬垫下方留下第一衬垫的底部上的第一衬垫的底部的材料。 第三蚀刻从栅极腔去除第二衬垫，在栅极腔中留下第一衬里的L形间隔物。 永久性栅极介电层和置换栅极形成在栅极腔中。

公开(公告)号：US20150031178A1

公开(公告)日：2015-01-29

申请号：US13950909

申请日：2013-07-25

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean RILEY ,  Seung-Chul SONG

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.

Abstract translation: 可以通过形成双层硬掩模来形成包含PMOS晶体管的集成电路。 硬掩模的第一层是使用烃试剂形成的含碳氮化硅。 硬掩模的第二层是使用氯化硅烷试剂在第一层上形成的含氯氮化硅。 在形成SiGe外延源极/漏极区之后，使用湿法蚀刻去除硬掩模，其以比第一层至少三倍的速率除去第二层。

公开(公告)号：US20150031177A1

公开(公告)日：2015-01-29

申请号：US13950842

申请日：2013-07-25

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean RILEY ,  Seung-Chul SONG

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

Abstract translation: 可以通过形成双层硬掩模来形成包含PMOS晶体管的集成电路。 硬掩模的第一层是使用卤化硅烷试剂形成的含卤素的氮化硅。 硬掩模的第二层是使用无卤试剂在第一层上形成的氮化硅。 在PMOS晶体管中蚀刻源极/漏极空腔之后，进行具有氢的预外延烘烤。 在形成SiGe外延源极/漏极区之后，去除硬掩模。