公开(公告)号：US20250045208A1

公开(公告)日：2025-02-06

申请号：US18394629

申请日：2023-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sverre BRUBAK ,  Ruchi SHANKAR ,  Praveen KUMAR N

IPC: G06F12/14

Abstract: An apparatus includes: a hardware security module; a processor; a memory subsystem; and a controller. The memory subsystem includes a write interface and a memory. The memory includes a first region that is a one-time programmable (OTP) region, and a second region that is a shared region. The controller is between the hardware security module, the processor, and the memory subsystem. The controller is configured to: receive an OTP write request from the hardware security module; inhibit the providing of shared memory operations by the processor responsive to the OTP write request and an acknowledgment from the processor; cause OTP data related to the OTP write request to be written to the first region of the memory; clear storage of the write interface after writing the OTP data is complete; and cease to inhibit the providing of shared memory operations after the storage of the write interface is cleared.