公开(公告)号：US20250045208A1

公开(公告)日：2025-02-06

申请号：US18394629

申请日：2023-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sverre BRUBAK ,  Ruchi SHANKAR ,  Praveen KUMAR N

IPC: G06F12/14

Abstract: An apparatus includes: a hardware security module; a processor; a memory subsystem; and a controller. The memory subsystem includes a write interface and a memory. The memory includes a first region that is a one-time programmable (OTP) region, and a second region that is a shared region. The controller is between the hardware security module, the processor, and the memory subsystem. The controller is configured to: receive an OTP write request from the hardware security module; inhibit the providing of shared memory operations by the processor responsive to the OTP write request and an acknowledgment from the processor; cause OTP data related to the OTP write request to be written to the first region of the memory; clear storage of the write interface after writing the OTP data is complete; and cease to inhibit the providing of shared memory operations after the storage of the write interface is cleared.

公开(公告)号：US20240134548A1

公开(公告)日：2024-04-25

申请号：US18389989

申请日：2023-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shobhit SINGHAL ,  Ruchi SHANKAR ,  Sverre BRUBAEK ,  Praveen KUMAR N

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.

公开(公告)号：US20230244396A1

公开(公告)日：2023-08-03

申请号：US17590884

申请日：2022-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shobhit SINGHAL ,  Ruchi SHANKAR ,  Sverre BRUBAEK ,  Praveen KUMAR N

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.