公开(公告)号：US10148288B2

公开(公告)日：2018-12-04

申请号：US15686361

申请日：2017-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yaoyu Tao ,  Joyce Kwong

IPC: H03M13/11

Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

公开(公告)号：US09793923B2

公开(公告)日：2017-10-17

申请号：US14950659

申请日：2015-11-24

Applicant: Texas Instruments Incorporated

Inventor： Yaoyu Tao ,  Joyce Kwong

IPC: H04L1/00 ,  H03M13/11

CPC classification number: H03M13/1117 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1142 ,  H03M13/116

Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

公开(公告)号：US20170353194A1

公开(公告)日：2017-12-07

申请号：US15686361

申请日：2017-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yaoyu Tao ,  Joyce Kwong

IPC: H03M13/11

CPC classification number: H03M13/1117 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1142 ,  H03M13/116

Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

公开(公告)号：US20170149446A1

公开(公告)日：2017-05-25

申请号：US14950659

申请日：2015-11-24

Applicant: Texas Instruments Incorporated

Inventor： Yaoyu Tao ,  Joyce Kwong

IPC: H03M13/11

CPC classification number: H03M13/1117 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1142 ,  H03M13/116

Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.