公开(公告)号：US10068631B2

公开(公告)日：2018-09-04

申请号：US14794560

申请日：2015-07-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy

IPC: G06F21/00 ,  G11C11/22 ,  H04L9/08 ,  H01L27/11507

Abstract: Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.

公开(公告)号：US10148288B2

公开(公告)日：2018-12-04

申请号：US15686361

申请日：2017-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yaoyu Tao ,  Joyce Kwong

IPC: H03M13/11

Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

公开(公告)号：US20160365510A1

公开(公告)日：2016-12-15

申请号：US15189114

申请日：2016-06-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy ,  Stephen Heinrich-Barna

IPC: H01L43/12 ,  H01L27/115 ,  H01L21/66 ,  G11C11/22

CPC classification number: H01L43/12 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2211/4013 ,  H01L22/14 ,  H01L27/115

Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

Abstract translation: 要永久打印在存储器阵列的存储单元中的只读（“RO”）数据被写入存储器阵列。 然后将一个或多个过应力条件（例如热，过电压，过电流和/或机械应力）施加到存储器阵列或存储器阵列内的各个存储单元。 过应力条件作用于存储单元的一个或多个状态确定元件以压印RO数据。 过应力条件永久地改变状态确定元件的状态确定属性的值，而不会使存储单元的正常操作失效。 状态确定属性的改变值根据RO数据位的状态来偏移单元。 该偏置在细胞读出信号中是可检测的。 预制的铁电随机存取存储器（“FRAM”）阵列被烘烤。 烘焙陷阱电偶极子在与预写数据的状态相对应的方向上取向，并形成了RO数据压印。

公开(公告)号：US09401196B1

公开(公告)日：2016-07-26

申请号：US14737247

申请日：2015-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy ,  Stephen K. Heinrich-Barna

IPC: G11C11/22

CPC classification number: H01L43/12 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2211/4013 ,  H01L22/14 ,  H01L27/115

Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

Abstract translation: 要永久打印在存储器阵列的存储单元中的只读（“RO”）数据被写入存储器阵列。 然后将一个或多个过应力条件（例如热，过电压，过电流和/或机械应力）施加到存储器阵列或存储器阵列内的各个存储单元。 过应力条件作用于存储单元的一个或多个状态确定元件以压印RO数据。 过应力条件永久地改变状态确定元件的状态确定属性的值，而不会使存储单元的正常操作失效。 状态确定属性的改变值根据RO数据位的状态来偏移单元。 该偏置在细胞读出信号中是可检测的。 预制的铁电随机存取存储器（“FRAM”）阵列被烘烤。 烘焙陷阱电偶极子在与预写数据的状态相对应的方向上取向，并形成了RO数据压印。

公开(公告)号：US09793923B2

公开(公告)日：2017-10-17

申请号：US14950659

申请日：2015-11-24

Applicant: Texas Instruments Incorporated

Inventor： Yaoyu Tao ,  Joyce Kwong

IPC: H04L1/00 ,  H03M13/11

CPC classification number: H03M13/1117 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1142 ,  H03M13/116

Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

公开(公告)号：US09711715B2

公开(公告)日：2017-07-18

申请号：US15189114

申请日：2016-06-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy ,  Stephen Heinrich-Barna

IPC: G11C11/22 ,  H01L43/12 ,  H01L21/66 ,  H01L27/115

CPC classification number: H01L43/12 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2211/4013 ,  H01L22/14 ,  H01L27/115

Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

公开(公告)号：US20170126414A1

公开(公告)日：2017-05-04

申请号：US14925662

申请日：2015-10-28

Applicant: Texas Instruments Incorporated

Inventor： Manish Goel ,  Joyce Kwong

IPC: H04L9/32 ,  G06F3/06 ,  G06F12/14 ,  H04L9/08

CPC classification number: H04L9/3278 ,  G06F3/0622 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/1408 ,  G06F2212/1052 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3242 ,  H04L2209/12

Abstract: Methods and a device for providing for authentication of an integrated circuit (IC) chip are shown. The IC chip contains a physically unclonable function (PUF), a processor, a non-volatile memory, and an encryption module containing first instructions that, when executed by the processor, receive the unique key from the PUF, receive a master key from an external source, encrypt the unique key using the master key and store the encrypted unique key in the non-volatile memory.

公开(公告)号：US20170011790A1

公开(公告)日：2017-01-12

申请号：US14794560

申请日：2015-07-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy

IPC: G11C11/22 ,  H04L9/08 ,  H01L27/115

CPC classification number: G11C11/2295 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  H01L27/11507 ,  H04L9/3278

Abstract: Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.

Abstract translation: 包含物理不可克隆功能（“PUF”）模式的只读（“RO”）数据被写入铁电随机存取存储器（“FRAM”）存储器阵列。 烘烤FRAM阵列以打印具有所选择的平均印刷深度和相应的平均读取可靠性的PUF图案。 在烘烤后的测试期间确定平均印痕深度和相应的平均读取可靠性将烘烤后读取的PUF图案与烘烤前书写的PUF图案进行比较可以进行其它PUF图案书写和烘烤循环，直到平均印痕深度 并且相关的读取可靠性达到第一选定的级别。 被确定为超过第二选定电平的印刷电路的集成电路可能被拒绝。 选择第一和第二级PUF图案印记，以便为每个含有FRAM阵列的集成电路产生具有唯一指纹的FRAM阵列。

公开(公告)号：US12050495B2

公开(公告)日：2024-07-30

申请号：US17130076

申请日：2020-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Clive Bittlestone ,  Joyce Kwong ,  Manish Goel

IPC: G06F1/26 ,  G06F21/73 ,  H04L9/32

CPC classification number: G06F1/26 ,  G06F21/73 ,  H04L9/3278

Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array.

公开(公告)号：US10541016B2

公开(公告)日：2020-01-21

申请号：US16120107

申请日：2018-08-31

Applicant: Texas Instruments Incorporated

Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy

IPC: G06F21/00 ,  G11C11/22 ,  H04L9/32 ,  H01L27/11507

Abstract: Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.