公开(公告)号：US20140223047A1

公开(公告)日：2014-08-07

申请号：US14015561

申请日：2013-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATION

Inventor： Balatripura Sodemma CHAVALI ,  Karl Friedrich GREB ,  Rajeev SUVARNA

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F12/1416 ,  G06F12/1458 ,  G06F12/1483 ,  G06F13/1605 ,  G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1052

Abstract: A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.

Abstract translation: 系统包括一个不可编程总线主机。 非可编程总线主机包括一个存储器保护单元（MPU），以在具有第一组访问权限的第一配置和具有第二组访问许可的第二配置和硬件逻辑中操作。 硬件逻辑执行第一任务和第二任务。 任务生成事务，硬件逻辑在执行第一和第二任务之间切换。 当硬件逻辑执行第一任务时，硬件逻辑还使得MPU在第一配置中操作，并且当硬件逻辑执行第二任务时使得MPU在第二配置中操作。