公开(公告)号：US20190007046A1

公开(公告)日：2019-01-03

申请号：US15635924

申请日：2017-06-28

Applicant: Texas Instruments Incorporation

Inventor： Christopher Michael Graves

IPC: H03K19/0185 ,  H03K19/00 ,  H03K17/16

Abstract: A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.

公开(公告)号：US20140125389A1

公开(公告)日：2014-05-08

申请号：US13754543

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATION

Inventor： Adam L. Shook

IPC: H03K5/12

CPC classification number: H03K19/00361 ,  G05F3/16 ,  H03K5/12 ,  H03K19/00384

Abstract: An apparatus, comprising: a PMOS current mirror have a first PFET and a second PFET coupled at their respective gates; a first current source coupled to drain of the first PFET; a second current source configured to have a current that is greater than the first current source, coupled to the drain of the second PFET; a capacitor coupled to the gates of the PFET current mirror; a third PFET gate-coupled to the current mirror; a driver NFET having a gate coupled to the drain of the third PFET, wherein a drain of the driver NFET is coupled to the capacitor.

Abstract translation: 一种装置，包括：PMOS电流镜，具有在其各自的栅极耦合的第一PFET和第二PFET; 耦合到所述第一PFET的漏极的第一电流源; 被配置为具有大于所述第一电流源的电流的第二电流源，耦合到所述第二PFET的漏极; 耦合到PFET电流镜的栅极的电容器; 栅极耦合到电流镜的第三PFET; 具有耦合到第三PFET的漏极的栅极的驱动器NFET，其中驱动器NFET的漏极耦合到电容器。

公开(公告)号：US20030152023A1

公开(公告)日：2003-08-14

申请号：US10060502

申请日：2002-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATION

Inventor： Srinath Hosur ,  Dennis Rauschmayer

IPC: H04J011/00 ,  H04B007/216

CPC classification number: H04L27/2602

Abstract: A wireless transmitter (TX1). The transmitter comprises circuitry for providing a plurality of control (CONTROL) bits and circuitry for providing a plurality of user (USER) bits. The transmitter also comprises circuitry for modulating (16) the plurality of control bits and the plurality of user bits into a stream of complex symbols and circuitry (18) for converting the stream of complex symbols into a parallel plurality of complex symbol streams. The transmitter also comprises circuitry (20) for performing an inverse fast Fourier transform on the parallel plurality of complex symbol streams to form a parallel plurality of OFDM symbols and circuitry (22) for converting the parallel plurality of OFDM symbols into a serial stream of OFDM symbols. Each OFDM symbol in the serial stream of OFDM symbols comprises a plurality of data points, and selected (SF2.x) OFDM symbols in the serial stream of OFDM symbols carry modulation information (AMOD). The modulation information in one or more of the selected OFDM symbols comprises a plurality of modulation groups, and the plurality of modulation groups comprises a number of modulation parameters that describe modulation of a corresponding set of data points in a subsequent OFDM symbol in the serial stream of OFDM symbols.

Abstract translation: 无线发射机（TX1）。 发射机包括用于提供多个控制（CONTROL）比特和用于提供多个用户（USER）比特）的电路的电路。 所述发射机还包括用于将所述多个控制比特和所述多个用户比特调制（16）为复数符号流和电路（18）的电路，用于将复符号流转换为并行多个复符号流。 发射机还包括用于对并行多个复符号流执行快速傅立叶逆变换的电路（20），以形成并行多个OFDM符号和电路（22），用于将并行多个OFDM符号转换成OFDM的串行流 符号。 OFDM符号的串行流中的每个OFDM符号包括多个数据点，并且在OFDM符号的串行流中选择的（SF2.x）OFDM符号携带调制信息（AMOD）。 所选择的OFDM符号中的一个或多个中的调制信息包括多个调制组，并且所述多个调制组包括多个调制参数，所述调制参数描述在串行流中随后的OFDM符号中对应的一组数据点的调制 的OFDM符号。

公开(公告)号：US20150348969A1

公开(公告)日：2015-12-03

申请号：US14725869

申请日：2015-05-29

Applicant: Texas Instruments Incorporation

Inventor： Henry Litzmann Edwards ,  Greg Charles Baldwin

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/12 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/15 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/122 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7391 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/7833 ,  H01L29/7836

Abstract: Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.

Abstract translation: 量子点接触的方法和装置。 在一种布置中，量子点接触装置包括半导体衬底的一部分中的至少一个阱区并掺杂到第一导电类型; 栅极结构，设置在所述半导体衬底的表面上; 栅极结构还包括形成在收缩区域中的量子点接触，所述收缩区域具有布置成使得最大尺寸小于等于约35纳米的预定距离的宽度和长度; 掺杂到与第一导电类型相反的第二导电类型的阱区中的漏极/源极区; 掺杂到第二导电类型的阱区中的源/漏区; 在所述至少一个阱区中的第一和第二轻掺杂漏极区。 公开了附加的方法和装置。

公开(公告)号：US20140223047A1

公开(公告)日：2014-08-07

申请号：US14015561

申请日：2013-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATION

Inventor： Balatripura Sodemma CHAVALI ,  Karl Friedrich GREB ,  Rajeev SUVARNA

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F12/1416 ,  G06F12/1458 ,  G06F12/1483 ,  G06F13/1605 ,  G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1052

Abstract: A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.

Abstract translation: 系统包括一个不可编程总线主机。 非可编程总线主机包括一个存储器保护单元（MPU），以在具有第一组访问权限的第一配置和具有第二组访问许可的第二配置和硬件逻辑中操作。 硬件逻辑执行第一任务和第二任务。 任务生成事务，硬件逻辑在执行第一和第二任务之间切换。 当硬件逻辑执行第一任务时，硬件逻辑还使得MPU在第一配置中操作，并且当硬件逻辑执行第二任务时使得MPU在第二配置中操作。

公开(公告)号：US20140167795A1

公开(公告)日：2014-06-19

申请号：US13714740

申请日：2012-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATION

Inventor： Joseph S. Mayfield ,  Chad R. Turner ,  Nolan B. Riley

IPC: G01R31/28

CPC classification number: G01R31/2874 ,  G01R31/2867

Abstract: Fault analysis of high power integrated circuits face thermal management challenges. This invention employs thermal diodes incorporated in the device undergoing fault analysis, and a closed loop microprocessor controlled feedback system for thermal control during test and fault analysis.

Abstract translation: 大功率集成电路故障分析面临热管理挑战。 本发明采用结合在经历故障分析的装置中的热二极管，以及用于在测试和故障分析期间进行热控制的闭环微处理器控制的反馈系统。