CACHE BANK MODELING WITH VARIABLE ACCESS AND BUSY TIMES
    1.
    发明申请
    CACHE BANK MODELING WITH VARIABLE ACCESS AND BUSY TIMES 失效
    具有可变访问和繁忙时间的高速缓存库建模

    公开(公告)号:US20110320729A1

    公开(公告)日:2011-12-29

    申请号:US12821891

    申请日:2010-06-23

    IPC分类号: G06F12/08 G06F12/00

    CPC分类号: G06F12/0895

    摘要: Various embodiments of the present invention manage access to a cache memory. In one embodiment, a set of cache bank availability vectors are generated based on a current set of cache access requests currently operating on a set of cache banks and at least a variable busy time of a cache memory includes the set of cache banks. The set of cache bank availability vectors indicate an availability of the set of cache banks. A set of cache access requests for accessing a set of given cache banks within the set of cache banks is received. At least one cache access request in the set of cache access requests is selected to access a given cache bank based on the a cache bank availability vectors associated with the given cache bank and the set of access request parameters associated with the at least one cache access that has been selected.

    摘要翻译: 本发明的各种实施例管理对高速缓冲存储器的访问。 在一个实施例中,基于当前在一组高速缓存组上操作的当前高速缓存访​​问请求集合来生成一组高速缓存存储库可用性向量,并且至少高速缓存存储器的可变繁忙时间包括该组高速缓冲存储器组。 该组缓存库可用性向量指示该组缓存存储体的可用性。 接收用于访问该组缓存组内的一组给定高速缓存存储体的一组缓存访问请求。 选择该组高速缓存访​​问请求中的至少一个高速缓存访​​问请求以基于与给定高速缓存组相关联的高速缓存存储体可用性向量和与该至少一个高速缓存访​​问相关联的一组访问请求参数访问给定高速缓存组 已被选中。