公开(公告)号：US6411980B2

公开(公告)日：2002-06-25

申请号：US77471301

申请日：2001-02-01

Applicant: TOSHIBA KK

Inventor： YOSHIDA TAKESHI

IPC: G06F5/01 ,  G06F7/50 ,  G06F7/76

CPC classification number: G06F7/507 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/764 ,  G06F2207/382 ,  G06F2207/3828

Abstract: Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in parallel. The mask signal generator generates the mask signal based on an amount of shift and split mode information. An output selector replaces data shifted by the shifter with code extension data bit by bit based on the mask signal, and outputs data which are shifted and code-extended according to the split mode information and arithmetic/logical shift information. In a carry-select type adder/subtractor as another embodiment, if split parallel process is to be executed, both a pair of unit adders/subtractors execute an arithmetic operation to be carried out for the case where no carry is supplied from lower digits, and then a selector selects an arithmetic result, which is obtained when no carry is supplied from lower digits, regardless of the carry from the lower digits.

Abstract translation: 并行地并行地进行输入数据的移位而不用移位器进行分割，代码扩展数据生成器的代码扩展数据的生成以及掩模信号发生器的掩蔽信号的生成。 屏蔽信号发生器基于移位量和分割模式信息产生屏蔽信号。 输出选择器基于掩码信号逐位地替换由移位器移位的代码扩展数据，并且根据分离模式信息和算术/逻辑移位信息输出被移位和代码扩展的数据。 在作为另一实施例的进位选择型加法器/减法器中，如果要执行分割并行处理，则一对单位加法器/减法器执行对于从低位指示不提供进位的情况下执行的算术运算， 然后选择器选择算术结果，该算术结果是当从低位数字提供进位时获得的，而与低位数字的进位无关。