公开(公告)号：US5831316A

公开(公告)日：1998-11-03

申请号：US778081

申请日：1997-01-02

申请人： Ta-Lee Yu ,  Konrad Young

发明人： Ta-Lee Yu ,  Konrad Young

IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/00

CPC分类号： H01L27/0277 ,  H01L27/088 ,  H01L29/7831 ,  H01L2924/0002

摘要： A multi-finger MOS transistor element is provided in which all of the base resistance values of parasitic bipolar transistors (NPN, if an NMOS, or PNP, if a PMOS transistor) in each finger MOS are equal to each other. Thus, each finger MOS transistor element in the multi-finger MOS transistor is turned on simultaneously to enhance ESD protection performance. In the multi-finger MOS transistor, the diffusion region for providing the well/substrate contact is distributed in the source region to make the base resistance value of the parasitic NPN (or PNP) transistor in each finger MOS equal to each other. The multi-finger MOS of the invention includes a plurality of drain regions, each having drain contacts, a plurality of source regions, each having source contacts, and a plurality of gate regions, wherein each gate region is between each drain region and the source region; a bias diffusion region formed in the source region along a middle line which is equally spaced between the pair of gate regions.

摘要翻译： 提供了多指MOS晶体管元件，其中每个指状MOS中的寄生双极晶体管（NPN，如果NMOS或PNP，如果PMOS晶体管）的所有基极电阻值彼此相等。 因此，多指MOS晶体管中的每个指状MOS晶体管元件同时导通，以增强ESD保护性能。 在多指MOS晶体管中，用于提供阱/衬底接触的扩散区域分布在源极区域中，以使每个手指MOS中的寄生NPN（或PNP）晶体管的基极电阻值彼此相等。 本发明的多指状MOS包括多个漏极区，每个具有漏极接触，多个源极区，每个具有源极接触，以及多个栅极区，其中每个栅极区在每个漏极区和源极之间 地区; 偏置扩散区，形成在沿着中间线的源极区中，所述中间线在所述一对栅极区之间间隔开。

公开(公告)号：US5889309A

公开(公告)日：1999-03-30

申请号：US770650

申请日：1996-12-19

申请人： Ta-Lee Yu ,  Chau-Neng Wu ,  Ling-Yen Yeh ,  Frank S-T Lin ,  Konrad Young

发明人： Ta-Lee Yu ,  Chau-Neng Wu ,  Ling-Yen Yeh ,  Frank S-T Lin ,  Konrad Young

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L23/62

CPC分类号： H01L27/0259 ,  H01L27/0658

摘要： An electrostatic discharge protection circuit formed in a semiconductor substrate includes a vertical bipolar junction transistor having a base which is grounded, an emitter connected to an output/input bonding pad of an integrated circuit, and a collector connected to a high power source via a resistor. The resistor is a parasitic resistor created by controlling the distance between the diffusion regions or the distance between a p-type well region and an n-type well region or formed by a lightly doped diffusion region in the semiconductor substrate to prevent current crowding and increase electrostatic protection.

摘要翻译： 形成在半导体衬底中的静电放电保护电路包括：具有接地的基极的垂直双极结型晶体管，连接到集成电路的输出/输入接合焊盘的发射极和经由电阻器连接到高功率源的集电极 。 电阻器是通过控制扩散区域之间的距离或p型阱区域和n型阱区域之间的距离或由半导体衬底中的轻掺杂扩散区域形成的寄生电阻器，以防止电流拥挤并增加 静电保护。

公开(公告)号：US20050033622A1

公开(公告)日：2005-02-10

申请号：US10636439

申请日：2003-08-06

申请人： Jacky Kuo ,  Albert Chang ,  K. P. Lee ,  Konrad Young ,  S. S. Lin ,  David Lai

发明人： Jacky Kuo ,  Albert Chang ,  K. P. Lee ,  Konrad Young ,  S. S. Lin ,  David Lai

IPC分类号： G06Q10/00 ,  G06F17/60

CPC分类号： G06Q10/109

摘要： A computer implemented method uses a system (100) for managing meetings. The system (100) has, a database (104) with data fields for entering a meeting definition of a future meeting as meeting definition data; a computer memory (106) storing the data for retrieval by the database (104); and an auto-mailer (108) sending an encrypted and read only meeting definition document and meeting reminders that are generated by the database (104) and sent by the auto-mailer (108) to notify meeting members identified by the data about a future meeting described by the data.

摘要翻译： 计算机实现的方法使用系统（100）来管理会议。 系统（100）具有数据库（104），其具有用于输入未来会议的会议定义的数据字段作为会议定义数据; 存储由数据库（104）检索的数据的计算机存储器（106）; 以及自动发送器（108），发送加密且只读的会议定义文档，并且会议由数据库（104）生成并由自动邮件（108）发送的提醒，以通知由关于未来的数据识别的会议成员 会议由数据描述。

公开(公告)号：US06323097B1

公开(公告)日：2001-11-27

申请号：US09590183

申请日：2000-06-09

申请人： Shien-Yang Wu ,  Tseng Chin Lo ,  Konrad Young

发明人： Shien-Yang Wu ,  Tseng Chin Lo ,  Konrad Young

IPC分类号： H01L2120

CPC分类号： H01L22/32 ,  G01B7/003 ,  H01L22/34

摘要： A method and structure is disclosed to measure spacing and misalignment of features in semiconductor integrated circuits. Three equally spaced, parallel first level conductive lines are formed on a first insulating layer with staircase patterns projecting both out of and into the inner edges of the outer lines. A second insulating layer is deposited and step contact vias are opened through the second insulating layer over the steps of the staircase patterns. The inner edge of the step contact via coincides with the inner edge of the step. Contact pad vias are opened through the second insulating layer over the outer lines and the step contact vias and the contact pad vias are filled with conductive material. A second level conductive line is formed over the second insulating layer parallel to said first level conductive lines and above the central first level conductive line. Resistor ladder patterns are formed projecting from both edges of said second level conductive line, the rungs of said ladder patterns being of equal length and being composed of rung conductive sections with a resistor section interposed. A center conductor contact pad is formed electrically connected to the second level conductive line. A right conductor contact pad is formed over the right contact pad via and a left conductor contact pad is formed over the left contact pad via. The resistances between the center conductor pad and the right conductor pad and between the center conductor pad and left conductor pad are measured. From these resistances are inferred which rungs of the resistor ladder patterns make contact with step contact vias of the outer first level conductive lines. This infers bounds for the distances, SR and SL, from the right and left outer first level conductive lines to the second level conductive line. Spacing and misalignment are calculated from these distances.

摘要翻译： 公开了一种用于测量半导体集成电路中的特征的间隔和未对准的方法和结构。 在第一绝缘层上形成三个等间隔的平行的第一级导电线，该第一绝缘层具有从外线的内边缘突出并进入外线的内边缘的阶梯图案。 沉积第二绝缘层，并且在台阶图案的台阶上通过第二绝缘层打开阶梯接触通孔。 台阶接触孔的内边缘与台阶的内边缘重合。 接触焊盘通孔在外线上通过第二绝缘层打开，并且步骤接触通孔和接触焊盘通孔填充有导电材料。 第二级导电线形成在平行于所述第一级导电线并且在中心第一级导电线上方的第二绝缘层上。 电阻梯形图案从所述第二电平导线的两个边缘突出形成，所述梯形图案的梯级具有相等的长度，并且由插入有电阻器部分的梯形导电部分组成。 形成电连接到第二电平导线的中心导体接触焊盘。 在右接触焊盘上形成右导体接触焊盘，并且在左接触焊盘通孔上形成左导体接触焊盘。 测量中心导体焊盘和右导体焊盘之间以及中心导体焊盘和左导体焊盘之间的电阻。 从这些电阻推断出电阻梯形图案的哪个梯级与外部第一级导电线的阶跃接触通孔接触。 这推断了从左右外一级导线到第二级导线的距离SR和SL。 从这些距离计算间距和不对中。