公开(公告)号：US20070025174A1

公开(公告)日：2007-02-01

申请号：US11470826

申请日：2006-09-07

申请人： Tae-Jung LEE ,  Byung-Sun KIM ,  Joon-Hung LEE

发明人： Tae-Jung LEE ,  Byung-Sun KIM ,  Joon-Hung LEE

IPC分类号： G11C8/00

CPC分类号： H01L27/1104 ,  G09G3/3611 ,  G11C7/02 ,  G11C8/16 ,  G11C11/4125 ,  H01L27/11

摘要： A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

摘要翻译： 提供了包括PMOS扫描晶体管的双端口半导体存储器件。 双端口半导体存储器件包括两个PMOS晶体管，两个NMOS下拉晶体管，两个NMOS传输晶体管和PMOS扫描晶体管。 作为PMOS的扫描晶体管，可以提高噪声容限。 此外，这七个晶体管排列在两个n阱和2个p阱中，而n阱和p阱以串联和交替的方式排列。 因此，沿着存储单元的短轴的存储单元的长度相对较短。 该存储单元布局通过将一对位线与阱边界并排布置，即在存储单元的短轴方向上有助于缩短位线的长度，并且可以防止位线与位线之间的串扰 通过在位线和互补位线之间布置导线来补充位线。

公开(公告)号：US20090290417A1

公开(公告)日：2009-11-26

申请号：US12348185

申请日：2009-01-02

申请人： Myoung-Kyu PARK ,  Byung-Sun KIM ,  Tae-Jung LEE ,  Dong-Ryul CHANG

发明人： Myoung-Kyu PARK ,  Byung-Sun KIM ,  Tae-Jung LEE ,  Dong-Ryul CHANG

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  G11C2216/10 ,  H01L27/11558

摘要： A nonvolatile memory device including a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of memory cells corresponding to intersections of the word lines and the bit lines; a common control gate line commonly connected to the memory cells; and a common erasing gate line commonly connected to the memory cells.

摘要翻译： 一种包括多个字线的非易失性存储器件; 与字线相交的多个位线; 对应于字线和位线的交点的多个存储单元; 通常连接到存储器单元的公共控制栅极线; 以及通常连接到存储器单元的公共擦除栅极线。

公开(公告)号：US20120138441A1

公开(公告)日：2012-06-07

申请号：US13117268

申请日：2011-05-27

申请人： Byung-Sun KIM ,  Min-Su JUNG ,  Cheol-Hee KIM

发明人： Byung-Sun KIM ,  Min-Su JUNG ,  Cheol-Hee KIM

IPC分类号： H01H13/76

CPC分类号： H01H13/705 ,  H01H2221/056 ,  H01H2223/036 ,  H01H2231/022 ,  H01H2233/03 ,  H04M1/23

摘要： A keypad assembly includes an operation member deformed according to user's manipulation to operate key switches, a binding member disposed on a top surface of the operation member, binding pieces extending and bent from the binding member to enclose sides of the operation member on an edge of the binding member, and a manipulation member disposed on a top surface of the binding member, the manipulation member including at least one key tops, in which the binding members are bound onto inner side walls of a housing of the portable terminal.

摘要翻译： 键盘组件包括根据用户的操纵而变形以操作键开关的操作构件，设置在操作构件的顶表面上的装订构件，从装订构件延伸和弯曲的绑定件，以将操作构件的侧面包围在操作构件的边缘上 装订构件和设置在装订构件的顶表面上的操纵构件，操纵构件包括至少一个键顶，其中装订构件被绑定到便携式终端的壳体的内侧壁上。