专利检索 ap:("Taejoong Song" OR "Sanghoon Baek" OR "Sungwe Cho" OR "Jung-Ho Do" OR "Giyoung Yang" OR "Jinyoung Lim") AND inv:"Sungwe Cho" 第 1 页

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发明授权
Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semicondutor device using the same 有权

公开(公告)号：US09928333B2

公开(公告)日：2018-03-27

申请号：US15184227

申请日：2016-06-16

申请人： Taejoong Song , Sanghoon Baek , Sungwe Cho , Jung-Ho Do , Giyoung Yang , Jinyoung Lim

发明人： Taejoong Song , Sanghoon Baek , Sungwe Cho , Jung-Ho Do , Giyoung Yang , Jinyoung Lim

IPC分类号： G06F17/50 , H01L27/02 , H01L27/118

CPC分类号： G06F17/5077 , H01L27/0207 , H01L27/11807

摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.