公开(公告)号：US5257230A

公开(公告)日：1993-10-26

申请号：US565820

申请日：1990-08-13

申请人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

发明人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

IPC分类号： H01L21/82 ,  G11C29/00 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  G11C17/16

CPC分类号： G11C29/785 ,  H01L23/5256 ,  H01L27/1126 ,  H01L2924/0002

摘要： There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential. Such a high threshold voltage is obtained by including in manufacture of the memory cell the steps of implanting impurity ions of a first conductivity type to the channel area of a region on the surface of a semiconductor substrate where transistors including the second transistor of a second conductivity type different from the first conductivity type are formed; and implanting impurity ions of the one conductivity type to the channel area of the second transistor and to the channel area of transistors of a conductivity type different from the second transistor; whereby the impurity ions are implanted twice to the channel area of the second transistor.

公开(公告)号：US5208780A

公开(公告)日：1993-05-04

申请号：US731467

申请日：1991-07-17

申请人： Taira Iwase ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuhiko Nobori

发明人： Taira Iwase ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuhiko Nobori

IPC分类号： G11C17/16 ,  G11C29/00

CPC分类号： G11C29/835 ,  G11C17/16

摘要： In an electrically programmable ROM, each cell 13 includes a series-connected element composed of a combination writing and reading transistor 17 and a fuse 15. One end of this series-connected element is connected to a corresponding bit line 19, and the other end thereof is grounded. A gate of the transistor 17 of the series-connected element is connected to a corresponding word line 23. Each bit line 19 is connected to a high-voltage applying pad 21 via an element such as diode or transistor provided with electrically connecting/isolating functions. When a data is written in the memory cell 13, the high-voltage applying pad 21 is electrically connected to the bit line 19. Under these conditions, if a high voltage is applied to the high-voltage applying pad 21, the transistor 17 performs snap-back action (i.e. secondary breakdown) to blow out the fuse 15. When the data is read, the high-voltage applying pad 21 is isolated from the bit line 19 without exerting influence upon the read out operation. In addition, in the above-mentioned electrically programmable ROM, a circuit for electrically blowing out the fuse by utilizing transistor's snap-back action is used as a redundancy signature indicative of whether the redundancy circuit is used or unused.

摘要翻译： 在电可编程ROM中，每个单元13包括由写入和读取晶体管17和熔丝15组成的串联元件。该串联元件的一端连接到对应的位线19，而另一端 它接地。 串联元件的晶体管17的栅极连接到相应的字线23.每个位线19经由诸如具有电连接/隔离功能的二极管或晶体管的元件连接到高压施加焊盘21 。 当数据被写入存储单元13时，高压施加焊盘21与位线19电连接。在这些条件下，如果向高压施加焊盘21施加高电压，则晶体管17执行 回扫动作（即二次击穿）以吹出保险丝15.当读取数据时，高压施加垫21与位线19隔离，而不会对读出操作产生影响。 此外，在上述电气可编程ROM中，使用用于通过利用晶体管的快速恢复动作来电熔熔丝的电路作为指示冗余电路是否被使用或未被使用的冗余标记。