公开(公告)号：US5257230A

公开(公告)日：1993-10-26

申请号：US565820

申请日：1990-08-13

申请人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

发明人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

IPC分类号： H01L21/82 ,  G11C29/00 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  G11C17/16

CPC分类号： G11C29/785 ,  H01L23/5256 ,  H01L27/1126 ,  H01L2924/0002

摘要： There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential. Such a high threshold voltage is obtained by including in manufacture of the memory cell the steps of implanting impurity ions of a first conductivity type to the channel area of a region on the surface of a semiconductor substrate where transistors including the second transistor of a second conductivity type different from the first conductivity type are formed; and implanting impurity ions of the one conductivity type to the channel area of the second transistor and to the channel area of transistors of a conductivity type different from the second transistor; whereby the impurity ions are implanted twice to the channel area of the second transistor.

公开(公告)号：US5208780A

公开(公告)日：1993-05-04

申请号：US731467

申请日：1991-07-17

申请人： Taira Iwase ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuhiko Nobori

发明人： Taira Iwase ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuhiko Nobori

IPC分类号： G11C17/16 ,  G11C29/00

CPC分类号： G11C29/835 ,  G11C17/16

摘要： In an electrically programmable ROM, each cell 13 includes a series-connected element composed of a combination writing and reading transistor 17 and a fuse 15. One end of this series-connected element is connected to a corresponding bit line 19, and the other end thereof is grounded. A gate of the transistor 17 of the series-connected element is connected to a corresponding word line 23. Each bit line 19 is connected to a high-voltage applying pad 21 via an element such as diode or transistor provided with electrically connecting/isolating functions. When a data is written in the memory cell 13, the high-voltage applying pad 21 is electrically connected to the bit line 19. Under these conditions, if a high voltage is applied to the high-voltage applying pad 21, the transistor 17 performs snap-back action (i.e. secondary breakdown) to blow out the fuse 15. When the data is read, the high-voltage applying pad 21 is isolated from the bit line 19 without exerting influence upon the read out operation. In addition, in the above-mentioned electrically programmable ROM, a circuit for electrically blowing out the fuse by utilizing transistor's snap-back action is used as a redundancy signature indicative of whether the redundancy circuit is used or unused.

摘要翻译： 在电可编程ROM中，每个单元13包括由写入和读取晶体管17和熔丝15组成的串联元件。该串联元件的一端连接到对应的位线19，而另一端 它接地。 串联元件的晶体管17的栅极连接到相应的字线23.每个位线19经由诸如具有电连接/隔离功能的二极管或晶体管的元件连接到高压施加焊盘21 。 当数据被写入存储单元13时，高压施加焊盘21与位线19电连接。在这些条件下，如果向高压施加焊盘21施加高电压，则晶体管17执行 回扫动作（即二次击穿）以吹出保险丝15.当读取数据时，高压施加垫21与位线19隔离，而不会对读出操作产生影响。 此外，在上述电气可编程ROM中，使用用于通过利用晶体管的快速恢复动作来电熔熔丝的电路作为指示冗余电路是否被使用或未被使用的冗余标记。

公开(公告)号：US5124948A

公开(公告)日：1992-06-23

申请号：US751574

申请日：1991-08-22

申请人： Makoto Takizawa ,  Taira Iwase ,  Masamichi Asano ,  Yasunori Arime

发明人： Makoto Takizawa ,  Taira Iwase ,  Masamichi Asano ,  Yasunori Arime

IPC分类号： G11C29/00

CPC分类号： G11C29/822

摘要： A main memory cell array is divided into a plurality of blocks, and a spare memory cell group is arranged apart from the main memory cell array. The spare memory cell group uses bit lines or word lines different from those of the main memory cell array and includes spare memory cells which are different in structure from the memory cells of the main memory cell array. The number of the memory cells of the spare memory cell group is the same as that of the main memory cells of one row or column in each block of the main memory cell array, and data can be programmed into the spare memory cells after the completion of the manufacturing process. The operation of programming data into the spare memory cells of the spare memory cell array is effected by use of a write-in address buffer and a write-in decoder. When a row or column including a defective memory cell is designated in the main memory cell array, the row or column of the spare memory cells in the spare memory cell group is activated.

摘要翻译： 主存储单元阵列被分成多个块，并且备用存储单元组被布置成与主存储单元阵列分开。 备用存储单元组使用与主存储单元阵列不同的位线或字线，并且包括与主存储单元阵列的存储单元结构不同的备用存储单元。 备用存储单元组的存储单元的数量与主存储单元阵列的每个块中的一个行或列的主存储单元的数量相同，并且可以在完成后将数据编程到备用存储单元中 的制造过程。 通过使用写入地址缓冲器和写入解码器来实现将数据编程到备用存储单元阵列的备用存储单元中的操作。 当在主存储单元阵列中指定包括有缺陷存储单元的行或列时，备用存储单元组中的备用存储单元的行或列被激活。

公开(公告)号：US07235829B2

公开(公告)日：2007-06-26

申请号：US11141024

申请日：2005-06-01

申请人： Makoto Takizawa

发明人： Makoto Takizawa

IPC分类号： H01L29/76

CPC分类号： H01L27/092 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/088 ,  H01L27/14643 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second conductivity type connected to an output terminal is formed on the semiconductor region. Further, a semiconductor region of a second conductivity type connected to the gate of the transistor is formed adjacent to the source/drain region of the transistor on the semiconductor region.

摘要翻译： 半导体集成电路器件包括第一导电类型的半导体区域。 在半导体区域上形成具有连接到输出端子的第二导电类型的源/漏区的第一绝缘栅场效应晶体管。 此外，与半导体区域上的晶体管的源极/漏极区域相邻地形成连接到晶体管的栅极的第二导电类型的半导体区域。

公开(公告)号：US5386381A

公开(公告)日：1995-01-31

申请号：US42676

申请日：1993-04-05

申请人： Makoto Takizawa ,  Kazunori Kanebako

发明人： Makoto Takizawa ,  Kazunori Kanebako

IPC分类号： G11C16/04 ,  G11C11/56 ,  H01L21/8246 ,  H01L27/112 ,  G11C17/00

CPC分类号： H01L27/112 ,  G11C11/5692

摘要： A mask ROM for storing multi-value data has a memory cell comprising a primary conductive region formed by a first conductive type semiconductor, a source region formed in the primary conductive region by a second conductive type semiconductor, a drain region formed in the primary conductive region by the second conductive type semiconductor, a channel region adjacently formed with the source region and the drain region, a gate insulation layer formed on the channel region, and a gate electrode formed on the gate insulation layer, wherein the channel region or the gate electrode is divided into a plurality of parts, each divided part having a different layer thickness from the other or a different transmissivity for ion injection, so as to form a ROM.

摘要翻译： 用于存储多值数据的掩模ROM具有存储单元，该存储单元包括由第一导电类型半导体形成的主导电区域，通过第二导电型半导体形成在第一导电区域中的源极区域，形成在第一导电型半导体区域中的漏极区域 通过第二导电型半导体形成的沟道区，与源极区和漏极区相邻形成的沟道区，形成在沟道区上的栅极绝缘层和形成在栅极绝缘层上的栅电极，其中沟道区或栅极 电极被分成多个部分，每个分割部分具有彼此不同的层厚度或用于离子注入的不同透射率，以便形成ROM。

公开(公告)号：US09265387B2

公开(公告)日：2016-02-23

申请号：US13641756

申请日：2011-02-14

申请人： Makoto Takizawa ,  Yuko Takizawa ,  Mayu Saita ,  Keiko Takizawa

发明人： Makoto Takizawa ,  Yuko Takizawa ,  Mayu Saita ,  Keiko Takizawa

IPC分类号： A47K11/02 ,  F23G5/10 ,  C02F11/06

CPC分类号： A47K11/023 ,  C02F11/06 ,  C02F2303/02 ,  F23G5/10 ,  Y02A50/454 ,  Y02W10/40

摘要： The present invention provides an electric incinerating toilet bowl and an incineration control method for the electric incinerating toilet bowl which can remove not only odor components but also smoke and soot generated when paper liners burn to thereby prevent the odor components and the smoke and soot from being exhausted. The incineration control method heats a smoke and soot removing filler layer to a smoke and soot removing temperature not lower than 350° C. by actuating a filler heating heater in response to input of a treatment start signal, carries out an incineration treatment by actuating an incinerating heater and an exhaust blower when a temperature of the smoke and soot removing filler layer has risen to a smoke and soot removing temperature, stops the incinerating heater and the filler heating heater when a temperature of an incineration chamber rises to a preset incineration treatment end temperature, and stops the exhaust blower when a temperature in the electric incinerating toilet bowl has dropped to a preset exhaust end temperature after the stop of the incinerating heater.

摘要翻译： 本发明提供一种用于电动焚烧马桶的电动焚烧马桶和焚烧控制方法，其不仅能消除气味成分，而且消除纸衬里燃烧时产生的烟雾和烟灰，从而防止气味成分和烟雾和烟灰 累。 焚烧控制方法通过根据输入处理开始信号来驱动填料加热器，将烟尘除烟填料层加热至不低于350℃的除烟和除烟温度，通过致动一个 焚烧加热器和排气鼓风机，当烟气和烟灰去除填料层的温度升高到烟雾和烟灰去除温度时，当焚化炉的温度上升到预设的焚化处理端时停止焚烧加热器和填料加热器 温度，并且当焚烧加热器停止后电动焚烧马桶的温度下降到预设的排气终点温度时停止排气鼓风机。

公开(公告)号：US20130031707A1

公开(公告)日：2013-02-07

申请号：US13641756

申请日：2011-02-14

申请人： Makoto Takizawa ,  Yuko Takizawa ,  Mayu Saita ,  Keiko Takizawa

发明人： Makoto Takizawa ,  Yuko Takizawa ,  Mayu Saita ,  Keiko Takizawa

IPC分类号： A47K11/02 ,  F23G5/00

CPC分类号： A47K11/023 ,  C02F11/06 ,  C02F2303/02 ,  F23G5/10 ,  Y02A50/454 ,  Y02W10/40

摘要： The present invention provides an electric incinerating toilet bowl and an incineration control method for the electric incinerating toilet bowl which can remove not only odor components but also smoke and soot generated when paper liners burn to thereby prevent the odor components and the smoke and soot from being exhausted. The incineration control method heats a smoke and soot removing filler layer to a smoke and soot removing temperature not lower than 350° C. by actuating a filler heating heater in response to input of a treatment start signal, carries out an incineration treatment by actuating an incinerating heater and an exhaust blower when a temperature of the smoke and soot removing filler layer has risen to a smoke and soot removing temperature, stops the incinerating heater and the filler heating heater when a temperature of an incineration chamber rises to a preset incineration treatment end temperature, and stops the exhaust blower when a temperature in the electric incinerating toilet bowl has dropped to a preset exhaust end temperature after the stop of the incinerating heater.

摘要翻译： 本发明提供一种用于电动焚烧马桶的电动焚烧马桶和焚烧控制方法，其不仅能消除气味成分，而且消除纸衬里燃烧时产生的烟雾和烟灰，从而防止气味成分和烟雾和烟灰 累。 焚烧控制方法通过根据输入处理开始信号来驱动填料加热器，将烟尘除烟填料层加热至不低于350℃的除烟和除烟温度，通过致动一个 焚烧加热器和排气鼓风机，当烟气和烟灰去除填料层的温度升高到烟雾和烟灰去除温度时，当焚化炉的温度上升到预设的焚化处理端时停止焚烧加热器和填料加热器 温度，并且当焚烧加热器停止后电动焚烧马桶的温度下降到预设的排气终点温度时停止排气鼓风机。

公开(公告)号：US20050281117A1

公开(公告)日：2005-12-22

申请号：US11153541

申请日：2005-06-16

申请人： Makoto Takizawa

发明人： Makoto Takizawa

IPC分类号： G11C5/02 ,  G11C8/00 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： G11C5/025 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526

摘要： A nonvolatile semiconductor memory device comprises, an internal memory cell array formed in internal area of a surface of semiconductor substrate, a row decoder and a column decoder formed in the internal area to select memory cell of the internal memory cell array, a peripheral circuit formed in the internal area to write and read a selected memory cell in the memory cell array, and external memory cell array formed in external area of the surface of the semiconductor substrate arranged beside the internal memory cell array and electrically separated from the internal memory cell array.

摘要翻译： 非易失性半导体存储器件包括形成在半导体衬底的表面的内部区域中的内部存储单元阵列，形成在内部区域中的行解码器和列解码器，以选择内部存储单元阵列的存储单元，形成外围电路 在内部区域中写入和读取存储单元阵列中的所选择的存储单元，以及形成在布置在内部存储单元阵列旁边的半导体衬底的表面的外部区域中并与内部存储单元阵列电隔离的外部存储单元阵列 。

公开(公告)号：US20050219781A1

公开(公告)日：2005-10-06

申请号：US11141024

申请日：2005-06-01

申请人： Makoto Takizawa

发明人： Makoto Takizawa

IPC分类号： H01L25/00 ,  G06K19/07 ,  H01L23/00 ,  H01L23/02 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/105 ,  H01L27/146 ,  H01L29/76 ,  H02H9/00

CPC分类号： H01L27/092 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/088 ,  H01L27/14643 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second conductivity type connected to an output terminal is formed on the semiconductor region. Further, a semiconductor region of a second conductivity type connected to the gate of the transistor is formed adjacent to the source/drain region of the transistor on the semiconductor region.

摘要翻译： 半导体集成电路器件包括第一导电类型的半导体区域。 在半导体区域上形成具有连接到输出端子的第二导电类型的源/漏区的第一绝缘栅场效应晶体管。 此外，与半导体区域上的晶体管的源极/漏极区域相邻地形成连接到晶体管的栅极的第二导电类型的半导体区域。

公开(公告)号：US08243539B2

公开(公告)日：2012-08-14

申请号：US12782159

申请日：2010-05-18

申请人： Makoto Takizawa ,  Shoichi Ozaki ,  Katsumi Abe

发明人： Makoto Takizawa ,  Shoichi Ozaki ,  Katsumi Abe

IPC分类号： G11C7/00

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C29/02 ,  G11C29/025 ,  G11C29/34 ,  G11C2029/1204

摘要： When bit lines or sense amplifiers are checked whether they are defective during a test performed to check whether the bit lines are defectively open, an electrical current supplied from one sense amplifier is detected by another sense amplifier. Thus, if plural bit lines are defectively open, they can be detected simultaneously. Consequently, the test time can be shortened greatly.

摘要翻译： 当检查位线或读出放大器在执行测试期间是否有缺陷以检查位线是否有缺陷时，由另一个读出放大器检测从一个读出放大器提供的电流。 因此，如果多个位线有缺陷，则可以同时检测。 因此，可以大大缩短测试时间。