公开(公告)号：US20220149178A1

公开(公告)日：2022-05-12

申请号：US17582860

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： CHENG-YI PENG ,  Song-Bor LEE

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417

Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions

公开(公告)号：US20190035691A1

公开(公告)日：2019-01-31

申请号：US15665230

申请日：2017-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： YASUTOSHI OKUNO ,  CHENG-YI PENG ,  ZIWEI FANG ,  I-MING CHANG ,  AKIRA MINEJI ,  YU-MING LIN ,  MENG-HSUAN HSIAO

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.