公开(公告)号：US20200168716A1

公开(公告)日：2020-05-28

申请号：US16590220

申请日：2019-10-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Wen-Hsing HSIEH ,  Wen-Yuan CHEN ,  Jon-Hsu HO ,  Song-Bor LEE ,  Bor-Zen TIEN

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L29/24 ,  H01L29/08 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.

公开(公告)号：US20210280486A1

公开(公告)日：2021-09-09

申请号：US16807305

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi PENG ,  Ching-Hua LEE ,  Song-Bor LEE

IPC: H01L23/31 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions

公开(公告)号：US20210273050A1

公开(公告)日：2021-09-02

申请号：US16806597

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi PENG ,  Song-Bor LEE

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/04 ,  H01L29/423

Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.

公开(公告)号：US20200176566A1

公开(公告)日：2020-06-04

申请号：US16596534

申请日：2019-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Ting TSAI ,  Chung-Wei HUNG ,  Jung-Ting CHEN ,  Ying-Hua LAI ,  Song-Bor LEE ,  Bor-Zen TIEN

IPC: H01L29/08 ,  H01L29/24

Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.

公开(公告)号：US20220149178A1

公开(公告)日：2022-05-12

申请号：US17582860

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： CHENG-YI PENG ,  Song-Bor LEE

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417

Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions

公开(公告)号：US20210280716A1

公开(公告)日：2021-09-09

申请号：US16807303

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi PENG ,  Song-Bor LEE

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions

公开(公告)号：US20230387302A1

公开(公告)日：2023-11-30

申请号：US18227712

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi PENG ,  Song-Bor LEE

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/0665 ,  H01L29/66636 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/41775 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/0673

Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions

公开(公告)号：US20220149155A1

公开(公告)日：2022-05-12

申请号：US17582866

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi PENG ,  Song-Bor LEE

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L29/10 ,  H01L29/04

Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions, Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.

公开(公告)号：US20160005650A1

公开(公告)日：2016-01-07

申请号：US14323496

申请日：2014-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Han-Wei YANG ,  Chen-Chung LAI ,  Song-Bor LEE

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L21/76895 ,  H01L21/76816 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure over a substrate and forming source and drain regions adjacent to the gate structure. The method also includes forming a first ILD layer surrounding the gate structure over the source and drain regions and forming a contact modulation structure over the gate structure. The method also includes etching the first ILD layer and the contact modulation structure to form a first contact trench over the source and drain regions and a second contact trench over the gate structure. The method further includes forming a first contact in the first contact trench and a second contact in the second contact trench. In addition, the first ILD layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate.

Abstract translation: 提供半导体结构及其形成方法。 该方法包括在衬底上形成栅极结构，并形成与栅极结构相邻的源区和漏区。 该方法还包括在源极和漏极区域上形成围绕栅极结构的第一ILD层，并在栅极结构上形成接触调制结构。 该方法还包括蚀刻第一ILD层和接触调制结构以在源极和漏极区域上形成第一接触沟槽，以及在栅极结构上方形成第二接触沟槽。 所述方法还包括在所述第一接触沟槽中形成第一接触和在所述第二接触沟槽中形成第二接触。 此外，第一ILD层具有第一蚀刻速率，并且接触调制结构具有小于第一蚀刻速率的第二蚀刻速率。