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Patent Agency Ranking
公开(公告)号：US20210375935A1
公开(公告)日：2021-12-02
申请号：US17133964
申请日：2020-12-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia Yu Ling , Chung-Te Lin , Katherine H. Chiang
IPC: H01L27/11597 , H01L27/11587 , H01L27/1159 , G11C11/22 , H01L29/06
Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.
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公开(公告)号：US20230027039A1
公开(公告)日：2023-01-26
申请号：US17818839
申请日：2022-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia Yu Ling , Chung-Te Lin , Katherine H. Chiang
IPC: H01L27/11597 , H01L27/11587 , H01L29/06 , G11C11/22 , H01L27/1159
Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.
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公开(公告)号：US12150306B2
公开(公告)日：2024-11-19
申请号：US17818839
申请日：2022-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia Yu Ling , Chung-Te Lin , Katherine H. Chiang
Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.
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公开(公告)号：US20240381657A1
公开(公告)日：2024-11-14
申请号：US18783709
申请日：2024-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia Yu Ling , Chung-Te Lin , Katherine H. Chiang
Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.
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公开(公告)号：US11716855B2
公开(公告)日：2023-08-01
申请号：US17133964
申请日：2020-12-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia Yu Ling , Chung-Te Lin , Katherine H. Chiang
CPC classification number: H10B51/20 , G11C11/2255 , G11C11/2257 , H01L29/0649 , H10B51/10 , H10B51/30
Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.
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