公开(公告)号：US20150074629A1

公开(公告)日：2015-03-12

申请号：US14542690

申请日：2014-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Sheng CHEN ,  Tsun-Yu YANG ,  Wei -Yi HU ,  Tao Wen CHUNG ,  Jui-Feng KUAN ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5045

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

Abstract translation: 一种用于电路设计的方法包括嵌入一个或多个参数化单元的寄生感知库。 寄生感知库用于将表示电路的一些但不是全部寄生效应的网络插入到电路原理图中，使单个电路原理图用于电路仿真，电路的寄生校验和LVS（布局与原理图）检查 。 电路设计过程只需要单一电路原理图，并形成掩模组。 识别单个电路原理图的关键路径，并提取寄生效应并将其插入原理图，使得能够执行寄生验证的预估计，并使用具有一些寄生效应的电路原理图进行LVS检查， 其中包括布局的所有寄生分量的后布局模拟。

公开(公告)号：US20140189623A1

公开(公告)日：2014-07-03

申请号：US13728295

申请日：2012-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Sheng CHEN ,  Tsun-Yu YANG ,  Wei-Yi HU ,  Tao Wen CHUNG ,  Jui-Feng KUAN ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5045

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

Abstract translation: 一种用于电路设计的方法包括嵌入一个或多个参数化单元的寄生感知库。 寄生感知库用于将表示电路的一些但不是全部寄生效应的网络插入到电路原理图中，使单个电路原理图用于电路仿真，电路的寄生校验和LVS（布局与原理图）检查 。 电路设计过程只需要单一电路原理图，并形成掩模组。 识别单个电路原理图的关键路径，并提取寄生效应并将其插入原理图，使得能够执行寄生验证的预估计，并使用具有一些寄生效应的电路原理图进行LVS检查， 其中包括布局的所有寄生分量的后布局模拟。