公开(公告)号：US20240021509A1

公开(公告)日：2024-01-18

申请号：US18358570

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L23/498 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76846

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US20240379521A1

公开(公告)日：2024-11-14

申请号：US18783669

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L23/498 ,  H01L21/762 ,  H01L21/768

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US11823989B2

公开(公告)日：2023-11-21

申请号：US17135435

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/498 ,  H01L21/762

CPC classification number: H01L23/49827 ,  H01L21/7684 ,  H01L21/76224 ,  H01L21/76846

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US20220020675A1

公开(公告)日：2022-01-20

申请号：US17135435

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/762

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.