公开(公告)号：US20210365625A1

公开(公告)日：2021-11-25

申请号：US17397684

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F30/398 ,  G06F30/394

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

公开(公告)号：US12039247B2

公开(公告)日：2024-07-16

申请号：US17397684

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F30/398 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/394

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

公开(公告)号：US11093683B2

公开(公告)日：2021-08-17

申请号：US16559097

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F30/398 ,  G06F30/394

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

公开(公告)号：US20240338510A1

公开(公告)日：2024-10-10

申请号：US18745854

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F30/398 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/394

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.