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公开(公告)号：US20210365625A1
公开(公告)日：2021-11-25
申请号：US17397684
申请日：2021-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-An Tien , Hsu-Ting Huang , Ru-Gun Liu
IPC: G06F30/398 , G06F30/394
Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.
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公开(公告)号：US10942443B2
公开(公告)日：2021-03-09
申请号：US16144882
申请日：2018-09-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hsu-Ting Huang , Shih-Hsiang Lo , Ru-Gun Liu
Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.
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公开(公告)号：US20180096094A1
公开(公告)日：2018-04-05
申请号：US15282131
申请日：2016-09-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsu-Ting Huang , Shuo-Yen Chou , Ru-Gun Liu
CPC classification number: G06F17/5081 , G03F1/70 , G03F1/78 , G06F2217/08
Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot mask and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. The SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.
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公开(公告)号：US20240338510A1
公开(公告)日：2024-10-10
申请号：US18745854
申请日：2024-06-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-An Tien , Hsu-Ting Huang , Ru-Gun Liu
IPC: G06F30/398 , G06F30/394
CPC classification number: G06F30/398 , G06F30/394
Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.
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公开(公告)号：US11429027B2
公开(公告)日：2022-08-30
申请号：US16534965
申请日：2019-08-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Shinn-Sheng Yu , Ru-Gun Liu , Hsu-Ting Huang , Chin-Hsiang Lin
Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.
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Patent Agency Ranking
公开(公告)号：US11360379B2
公开(公告)日：2022-06-14
申请号：US17121632
申请日：2020-12-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Fu An Tien , Hsu-Ting Huang , Ru-Gun Liu
Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.
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公开(公告)号：US11092899B2
公开(公告)日：2021-08-17
申请号：US16698044
申请日：2019-11-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hsu-Ting Huang , Tung-Chin Wu , Shih-Hsiang Lo , Chih-Ming Lai , Jue-Chin Yu , Ru-Gun Liu , Chin-Hsiang Lin
IPC: G06F30/398 , G06F30/392 , G03F7/20 , G06F16/23 , G06N3/08 , G06N3/04
Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.
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公开(公告)号：US12039247B2
公开(公告)日：2024-07-16
申请号：US17397684
申请日：2021-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-An Tien , Hsu-Ting Huang , Ru-Gun Liu
IPC: G06F30/398 , G06F30/394
CPC classification number: G06F30/398 , G06F30/394
Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.
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公开(公告)号：US11320747B2
公开(公告)日：2022-05-03
申请号：US17121542
申请日：2020-12-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Shinn-Sheng Yu , Ru-Gun Liu , Hsu-Ting Huang , Kenji Yamazoe , Minfeng Chen , Shuo-Yen Chou , Chin-Hsiang Lin
IPC: G03F7/20
Abstract: Photolithography apparatus includes a radiation source, a mask to modify radiation from the radiation source so the radiation exposes photoresist layer disposed on a semiconductor substrate in patternwise manner, a wafer stage, and a controller. The wafer stage supports the semiconductor substrate. The controller determines target total exposure dose for the photoresist layer and target focus position for the photoresist layer; and controls exposure of first portion of the photoresist layer to first exposure dose of radiation at first focus position using first portion of the mask, moving the semiconductor substrate relative to the mask; and exposure of the first portion of the photoresist layer to second exposure dose of radiation using second portion of the mask at second focus position, and exposure of second portion of the photoresist layer to the second exposure dose at the second focus position using the first portion of the mask.
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公开(公告)号：US09990460B2
公开(公告)日：2018-06-05
申请号：US15282131
申请日：2016-09-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsu-Ting Huang , Shuo-Yen Chou , Ru-Gun Liu
CPC classification number: G06F17/5081 , G03F1/70 , G03F1/78 , G06F2217/08
Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot mask and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. The SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.
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