公开(公告)号：US20230012621A1

公开(公告)日：2023-01-19

申请号：US17662364

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chuan YANG ,  Ruey-Wen CHANG ,  Feng-Ming CHANG ,  Kian-Long LIM ,  Kuo-Hsiu HSU ,  Lien Jung HUNG ,  Ping-Wei WANG

IPC: G11C11/417 ,  H01L27/11 ,  H01L29/423

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

公开(公告)号：US20170256548A1

公开(公告)日：2017-09-07

申请号：US15059021

申请日：2016-03-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Hsiu HSU ,  Chong-De LIEN

IPC: H01L27/11 ,  H01L27/105

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/1052 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.

公开(公告)号：US20230164971A1

公开(公告)日：2023-05-25

申请号：US18151991

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei WANG ,  Chih-Chuan YANG ,  Lien Jung HUNG ,  Feng-Ming CHANG ,  Kuo-Hsiu HSU ,  Kian-Long LIM ,  Ruey-Wen CHANG

IPC: H10B10/00 ,  H01L23/528 ,  H01L29/06 ,  G11C11/418 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H10B10/125 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/0673 ,  G11C11/418 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L29/42392

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US20180350820A1

公开(公告)日：2018-12-06

申请号：US16042304

申请日：2018-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Hsiu HSU ,  Chong-De LIEN

IPC: H01L27/11 ,  H01L27/105 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/1052 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.