公开(公告)号：US20190096474A1

公开(公告)日：2019-03-28

申请号：US15962409

申请日：2018-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao PAO ,  Kian-Long LIM ,  Feng-Ming CHANG ,  Lien-Jung HUNG

IPC: G11C11/412 ,  H01L27/02 ,  H01L27/11

Abstract: A static random access memory (SRAM) array is provided. The SRAM array includes a first bit cell array, a second bit cell array, and a strap cell. The second bit cell array is arranged along a first direction. The strap cell is arranged along a second direction and is positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes an H-shaped NW region, an H-shaped PW region, and a deep N-type well (DNW) region. The H-shaped NW region and the H-shaped PW region each includes two strip portions extending along the first direction and a linking portion extending along the second direction. Two terminals of the linking portion are in contact with the two strip portions.

公开(公告)号：US20230164971A1

公开(公告)日：2023-05-25

申请号：US18151991

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei WANG ,  Chih-Chuan YANG ,  Lien Jung HUNG ,  Feng-Ming CHANG ,  Kuo-Hsiu HSU ,  Kian-Long LIM ,  Ruey-Wen CHANG

IPC: H10B10/00 ,  H01L23/528 ,  H01L29/06 ,  G11C11/418 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H10B10/125 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/0673 ,  G11C11/418 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L29/42392

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US20200143874A1

公开(公告)日：2020-05-07

申请号：US16725409

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao PAO ,  Kian-Long LIM ,  Feng-Ming CHANG ,  Lien-Jung HUNG

IPC: G11C11/412 ,  H01L27/02 ,  H01L27/11

Abstract: A static random access memory (SRAM) array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction. The SRAM array includes a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The SRAM array includes a deep N-type well region underlying and connected to the first N-type well region and the second N-type well region.

公开(公告)号：US20210383859A1

公开(公告)日：2021-12-09

申请号：US17407005

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan CHANG ,  Kian-Long LIM ,  Jui-Lin CHEN ,  Feng-Ming CHANG

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

公开(公告)号：US20210366831A1

公开(公告)日：2021-11-25

申请号：US17303782

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan CHANG ,  Jui-Lin CHEN ,  Kian-Long LIM ,  Feng-Ming CHANG

IPC: H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/535

Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

公开(公告)号：US20210312997A1

公开(公告)日：2021-10-07

申请号：US16837227

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen SU ,  Kian-Long LIM ,  Wen-Chun KENG ,  Chang-Ta YANG ,  Shih-Hao LIN

IPC: G11C17/18 ,  H01L27/112 ,  G11C7/18

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

公开(公告)号：US20210287739A1

公开(公告)日：2021-09-16

申请号：US17332280

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kian-Long LIM ,  Chia-Hao PAO

IPC: G11C11/419 ,  G11C11/412

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a fist output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

公开(公告)号：US20210217467A1

公开(公告)日：2021-07-15

申请号：US16730376

申请日：2019-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan CHANG ,  Kian-Long LIM ,  Jui-Lin CHEN ,  Feng-Ming CHANG

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

公开(公告)号：US20210098055A1

公开(公告)日：2021-04-01

申请号：US16587504

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kian-Long LIM ,  Chia-Hao Pao

IPC: G11C11/419 ,  G11C11/412

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

公开(公告)号：US20200335155A1

公开(公告)日：2020-10-22

申请号：US16921156

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao PAO ,  Kian-Long LIM ,  Feng-Ming CHANG ,  Lien-Jung HUNG

IPC: G11C11/412 ,  H01L27/11 ,  H01L27/02

Abstract: A SRAM array is provided, including a first bit cell array and a second bit cell array arranged along a first direction; a strap cell arranged in a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first strap column, a second strap column, a doped P-type region, a doped N-type region, and a deep N-type well region. The first strap column includes a first P-type well region and two first N-type well regions adjacent opposite sides of the first P-type well region along the first direction. The second strap column is adjacent to the first strap column along the second direction. The second strap column includes a second N-type well region and two second P-type well regions adjacent opposite sides of the second N-type well region along the first direction.