公开(公告)号：US20250062232A1

公开(公告)日：2025-02-20

申请号：US18529948

申请日：2023-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chou Chiang ,  Chih-Yi Chang ,  Hung-Yi Huang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/06

Abstract: A method includes forming a conductive layer over a first dielectric layer; etching a recess in the conductive layer, wherein the recess exposes a top surface of the first dielectric layer; selectively depositing a capping layer on exposed sidewalls of the conductive layer within the recess; depositing a liner on the capping layer; forming a sacrificial material in the recess; and forming a second dielectric layer on the sacrificial material and on sidewalls of the recess; and after forming the second dielectric layer, performing a thermal process to remove the sacrificial material.