公开(公告)号：US20140262797A1

公开(公告)日：2014-09-18

申请号：US13858994

申请日：2013-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yi Chang ,  Liang-Yueh Ou Yang ,  Chen-Yuan Kao ,  Hung-Wen Su

IPC: C25D5/02 ,  C25D17/00 ,  C25D5/18

CPC classification number: C25D5/02 ,  C25D3/38 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/002 ,  C25D17/007 ,  C25D17/10 ,  H01L21/2885 ,  H01L21/76877

Abstract: The present disclosure relates to an electro-chemical plating (ECP) process which utilizes a dummy electrode as a cathode to perform plating for sustained idle times to mitigate additive dissociation. The dummy electrode also allows for localized plating function to improve product gapfill, and decrease wafer non-uniformity. A wide range of electroplating recipes may be applied with this strategy, comprising current plating up to approximately 200 Amps, localized plating with a resolution of approximately 1 mm, and reverse plating to remove material from the dummy electrode accumulated during the dummy plating process and replenish ionic material within the electroplating solution.

Abstract translation: 本发明涉及一种电化学电镀（ECP）工艺，其利用虚拟电极作为阴极来进行电镀以维持空闲时间以减轻附加离解。 虚拟电极还允许局部电镀功能，以改善产品间隙填充，并减少晶片的不均匀性。 可以应用这种策略的各种电镀配方，包括当前电镀高达约200安培，分辨率约为1mm的局部电镀，以及反电镀以从虚拟电镀过程中累积的虚拟电极中除去材料并补充 电镀液中的离子材料。

公开(公告)号：US11527476B2

公开(公告)日：2022-12-13

申请号：US17143496

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Min Liu ,  Chia-Pang Kuo ,  Chien Chung Huang ,  Chih-Yi Chang ,  Ya-Lien Lee ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.

公开(公告)号：US09632498B2

公开(公告)日：2017-04-25

申请号：US13870025

申请日：2013-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yi Chang ,  Liang-Yueh Ou Yang ,  Chen-Yuan Kao ,  Hung-Wen Su

IPC: G05B19/418 ,  H01L23/522 ,  H01L21/288 ,  H01L21/768

CPC classification number: G05B19/41835 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A computer-implemented system and method of compensating for filling material losses in a semiconductor process. The computer-implemented method includes determining using a computer a pattern density difference between a first circuit pattern above a semiconductor substrate and a second circuit pattern adjacent to the first pattern. A dummy pattern is inserted between the first pattern and the second pattern so as to compensate for an estimated loss of filling material induced during electrochemical plating by the pattern density difference exceeding a threshold pattern density difference.

公开(公告)号：US11810857B2

公开(公告)日：2023-11-07

申请号：US17001917

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Chih-Yi Chang ,  Ming-Hsiao Hsieh ,  Wei-Hsiang Chan ,  Ya-Lien Lee ,  Chien Chung Huang ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76877

Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.

公开(公告)号：US20220367266A1

公开(公告)日：2022-11-17

申请号：US17382001

申请日：2021-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Chih-Yi Chang ,  Wei Hsiang Chan ,  Chih-Chien Chi ,  Chi-Feng Lin ,  Hung-Wen Su

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

公开(公告)号：US20250062232A1

公开(公告)日：2025-02-20

申请号：US18529948

申请日：2023-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chou Chiang ,  Chih-Yi Chang ,  Hung-Yi Huang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/06

Abstract: A method includes forming a conductive layer over a first dielectric layer; etching a recess in the conductive layer, wherein the recess exposes a top surface of the first dielectric layer; selectively depositing a capping layer on exposed sidewalls of the conductive layer within the recess; depositing a liner on the capping layer; forming a sacrificial material in the recess; and forming a second dielectric layer on the sacrificial material and on sidewalls of the recess; and after forming the second dielectric layer, performing a thermal process to remove the sacrificial material.

公开(公告)号：US20220084937A1

公开(公告)日：2022-03-17

申请号：US17143496

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Min Liu ,  Chia-Pang Kuo ,  Chien Chung Huang ,  Chih-Yi Chang ,  Ya-Lien Lee ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.

公开(公告)号：US20240379430A1

公开(公告)日：2024-11-14

申请号：US18782460

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Chih-Yi Chang ,  Wei Hsiang Chan ,  Chih-Chien Chi ,  Chi-Feng Lin ,  Hung-Wen Su

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

公开(公告)号：US20230369224A1

公开(公告)日：2023-11-16

申请号：US18358803

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Chih-Yi Chang ,  Ming-Hsiao Hsieh ,  Wei-Hsiang Chan ,  Ya-Lien Lee ,  Chien Chung Huang ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76877 ,  H01L21/76804 ,  H01L21/76846

Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.

公开(公告)号：US20220068826A1

公开(公告)日：2022-03-03

申请号：US17001917

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chia-Pang Kuo ,  Chih-Yi Chang ,  Ming-Hsiao Hsieh ,  Wei-Hsiang Chan ,  Ya-Lien Lee ,  Chien Chung Huang ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768

Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.