公开(公告)号：US11056396B1

公开(公告)日：2021-07-06

申请号：US16728154

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US20240395628A1

公开(公告)日：2024-11-28

申请号：US18788006

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes providing a structure having a first channel member, a second channel member, and a third channel member, forming a first oxide layer, a second oxide layer, and a third oxide layer, the first oxide layer wrapping the first channel member, the second oxide layer wrapping the second channel member, the third oxide layer wrapping the third channel member, forming a first capping layer, a second capping layer, and a third capping layer over the first oxide layer, the second oxide layer, and the third oxide layer, respectively, removing the second capping layer, and after removing the second capping layer performing an oxide growing process to increase a thickness of the second oxide layer.

公开(公告)号：US12255105B2

公开(公告)日：2025-03-18

申请号：US17363837

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.

公开(公告)号：US20210327765A1

公开(公告)日：2021-10-21

申请号：US17363837

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.

公开(公告)号：US20210202323A1

公开(公告)日：2021-07-01

申请号：US16728154

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.