公开(公告)号：US12255105B2

公开(公告)日：2025-03-18

申请号：US17363837

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.

公开(公告)号：US12243871B2

公开(公告)日：2025-03-04

申请号：US18171530

申请日：2023-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Han Liu ,  Hoppy Lee ,  Chung-Yu Chiang ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L27/07 ,  H01L21/033 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L49/02

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

公开(公告)号：US11728373B2

公开(公告)日：2023-08-15

申请号：US17034459

申请日：2020-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Hsiao-Lan Yang ,  Chih-Yung Lin

IPC: H01L21/762 ,  H01L49/02 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/06 ,  H01L21/3105 ,  H01L29/78

CPC classification number: H01L28/60 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/0629 ,  H01L29/0649 ,  H01L21/31053 ,  H01L29/785

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.

公开(公告)号：US20210375697A1

公开(公告)日：2021-12-02

申请号：US17404443

申请日：2021-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Hui Hsu ,  Po-Nien Chen ,  Yi-Hsuan Chung ,  Bo-Shiuan Shie ,  Chih-Yung Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

公开(公告)号：US11127639B2

公开(公告)日：2021-09-21

申请号：US16547942

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhen Geng ,  Kitchun Kwong ,  Taicheng Shieh ,  Bo-Shiuan Shie ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a first, a second, a third, and a fourth fin structures over a substrate. The method also includes forming a first spacer layer over sidewalls of the first and the second fin structures. The method further includes forming a second spacer layer over the first spacer layer and sidewalls of the third and the fourth fin structures. In addition, the method includes forming a first blocking fin between the first and the second fin structures. The first blocking fin is separated from the first fin structure by portions of the first spacer layer and the second spacer layer. The method includes forming a second blocking fin between the third and the fourth fin structures. The second blocking fin is separated from the third fin structure by a portion of the second spacer layer.

公开(公告)号：US10700160B2

公开(公告)日：2020-06-30

申请号：US16512315

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chiun Lin ,  Po-Nien Chen ,  Chen Hua Tsai ,  Chih-Yung Lin

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L23/522 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US20230369387A1

公开(公告)日：2023-11-16

申请号：US18355072

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Hsiao-Lan Yang ,  Chih-Yung Lin

IPC: H01G4/228 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/762 ,  H01L29/06 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3105 ,  H01L29/78

CPC classification number: H01L28/60 ,  H01L21/823481 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0629 ,  H01L21/823431 ,  H01L21/76224 ,  H01L29/0649 ,  H01L23/5226 ,  H01L21/76897 ,  H01L23/528 ,  H01L21/31053 ,  H01L29/785

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.

公开(公告)号：US11056396B1

公开(公告)日：2021-07-06

申请号：US16728154

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US20210057286A1

公开(公告)日：2021-02-25

申请号：US16547942

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhen Geng ,  Kitchun Kwong ,  Taicheng Shieh ,  Bo-Shiuan Shie ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a first, a second, a third, and a fourth fin structures over a substrate. The method also includes forming a first spacer layer over sidewalls of the first and the second fin structures. The method further includes forming a second spacer layer over the first spacer layer and sidewalls of the third and the fourth fin structures. In addition, the method includes forming a first blocking fin between the first and the second fin structures. The first blocking fin is separated from the first fin structure by portions of the first spacer layer and the second spacer layer. The method includes forming a second blocking fin between the third and the fourth fin structures. The second blocking fin is separated from the third fin structure by a portion of the second spacer layer.

公开(公告)号：US20210013300A1

公开(公告)日：2021-01-14

申请号：US17034459

申请日：2020-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Hsiao-Lan Yang ,  Chih-Yung Lin

IPC: H01L49/02 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/06 ,  H01L21/762

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.