公开(公告)号：US10002802B2

公开(公告)日：2018-06-19

申请号：US15606098

申请日：2017-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Sheng-Tang Wang ,  Chia-Ming Chang ,  Shih-Che Lin ,  Chao-Jui Wang

IPC: H01L21/00 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining a tuning amount according to the differences between the gate lengths of each core, and adjusting at least one mask for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts.

公开(公告)号：US09666495B2

公开(公告)日：2017-05-30

申请号：US14105794

申请日：2013-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Tang Wang ,  Chia-Ming Chang ,  Shih-Che Lin ,  Chao-Jui Wang

IPC: H01L21/00 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining tuning amounts according to the differences between the gate lengths of each core, and adjusting manufacturing conditions for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts for reducing core-to-core mismatch due to the surrounding environment of each core. Each of the SOC products in the second lot includes more than two cores identical to each other and also identical to the cores in the first lot.