公开(公告)号：US10763338B2

公开(公告)日：2020-09-01

申请号：US15690693

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko Jang-Jian ,  Ting-Chun Wang ,  Chuan-Pu Liu

IPC: H01L29/45 ,  H01L29/66 ,  H01L21/768 ,  H01L21/326 ,  H01L21/285 ,  H01L29/78 ,  H01L29/417 ,  H01L29/165 ,  H01L29/08 ,  H01L21/02

Abstract: The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.